Messages in this thread | | | Date | Sun, 22 Nov 1998 12:42:12 +0100 (MET) | From | Gerard Roudier <> | Subject | Re: 2.1.125 - Problem. & Aic7xxx 5.1.0 |
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On Sat, 21 Nov 1998, Alan Cox wrote:
> > nowadays you should read them carefully. Even if host bridges may flush > > posted write buffers in some situations that are not required by PCI > > specs, how do you want that a full PCI bus hierarchy would have buffers > > flushed everywhere, since as you perhaps know, there is no side-band > > signals with PCI. > > Thats a detail I'd missed. Thats quite a nasty suprise in fact.
It is not a simple detail, I think, but something very important.
PCI device driver writers and maintainers must keep in mind that when a PCI read transaction issued from A to B completes at A, all posted writes issued before this PCI read on the A /to/from B path are guaranteed to have been flushed to their destination. (Only posted writes involving A -> B and/or B -> A have sometimes to be guaranteed so at some places of some PCI device drivers).
Obviously PCI transactions that go in the same direction are ordered. But 2 PCI transactions that go in opposite directions are not required to be so. Performing a PCI memory read is the only way to flush everything on the path between the C code and the PCI device. This read can be performed by either part (I mean the C code or the device) and must target the other part. If by luck or by design this read exists at the right place, no dummy read is needed, but if it does not, a dummy read must be performed each time we want posted transactions to be guaranteed to have completed at their destination.
Gerard.
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