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SubjectRe: 2.1.125 - Problem. & Aic7xxx 5.1.0
Date
> nowadays you should read them carefully. Even if host bridges may flush
> posted write buffers in some situations that are not required by PCI
> specs, how do you want that a full PCI bus hierarchy would have buffers
> flushed everywhere, since as you perhaps know, there is no side-band
> signals with PCI.

Thats a detail I'd missed. Thats quite a nasty suprise in fact.

> > iobarrier_w()
> > iobarrier_rw()
>
> Naming something the same does not mean that it is portable. In my

No but its a start to getting people to provide such implementations.

> > which are nops on a normal PC.
> Your normal PC is broken, in my opinion, or just different from mine. :-)

No I appear to be wrong about PCI. It happens - contrary to speculation
in some areas in human



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