On Wed, 02 Sep 2026 10:30:02 +0200
"Mathieu Dubois-Briand" <mathieu.dubois-briand@bootlin.com> wrote:

> On Wed Sep 2, 2026 at 8:26 AM CEST, Andreas Kemnade wrote:
> > Hi,
> >
> > this seems to produce on OMAP3 (DM3730), even with the init fix.
> >
> > [    0.000000] clocksource: 32k_counter: mask: 0xffffffff max_cycles: 0xffffffff
> > , max_idle_ns: 58327039986419 ns                                                
> > [    0.000030] sched_clock: 32 bits at 33kHz, resolution 30517ns, wraps every 65
> > 535999984741ns                                                                  
> > [    0.013488] clk: failed to reparent gpt1_fck to omap_32k_fck: -22            
> > [    0.019805] Failed to initialize '/ocp@68000000/target-module@48318000/timer@
> > 0': -19                                                                         
> >
> > Regards,
> > Andreas  
> 
> Hi Andreas,
> 
> That one will be a bit harder for me to debug, as I'm not sure I can
> easily get this hardware. But looking at the device tree and the
> reference manual, I suspect something is wrong in the omap3 device tree.
> 
> In omap3.dtsi, we have this node [1]:
> 
> &timer1_target {
> 	ti,no-reset-on-init;
> 	ti,no-idle;
> 	timer@0 {
> 		assigned-clocks = <&gpt1_fck>;
> 		assigned-clock-parents = <&omap_32k_fck>;
> 	};
> };
> 
> I suspect that's the source of the error: __set_clk_parents() in
> drivers/clk/clk-conf.c will try to set &omap_32k_fck as a parent of
> &gpt1_fck. But looking at omap3xxx-clocks.dtsi [2], &omap_32k_fck is not
> a valid parent:
> 
> 	gpt1_fck: gpt1_fck {
> 		#clock-cells = <0>;
> 		compatible = "ti,composite-clock";
> 		clocks = <&gpt1_gate_fck>, <&gpt1_mux_fck>;
> 	};
> 
the composite clock is meant to combine the two clocks into one,
so you have one single clock with enable/disable functions and
parents. At least that seems to be the idea.

If the system fully boots, you see:
localhost:/sys/kernel/debug/clk/gpt1_fck# cat clk_possible_parents 
omap_32k_fck sys_ck

> Yet the &gpt1_mux_fck is a mux, and one of the parent is indeed
> &omap_32k_fck [3]. So I suspect the correct assigned clock parent in
> timer@0 should be &gpt1_mux_fck.
> 
> Can you try it that way?
> 
[    0.000000] OMAP clocksource: 32k_counter at 32768 Hz                        
[    0.000000] clocksource: 32k_counter: mask: 0xffffffff max_cycles: 0xfffffffs
[    0.000000] sched_clock: 32 bits at 33kHz, resolution 30517ns, wraps every 6s
[    0.013458] dmtimer_systimer_setup: clock source init failed: -517           

The system does not boot much further.

> Now, I have doubts about how this was working correctly so far. You
> don't see any error at all without my changes?
> 
No error at all.

Regards,
Andreas