On Mon, Jun 29, 2026 at 12:50:53PM +0530, Santhosh Kumar K wrote:
> On TI K3 SoCs, DMA transfers from OSPI produce corrupted data when the
> source address is only 4-byte aligned (not 4K-aligned). The root cause
> is XIP read prefetch in the FSS_FSAS_GENREGS wrapper (SYSCONFIG.DISXIP,
> bit 7), which is enabled by default.
> 
> This series adds a dedicated FSS_FSAS platform driver that disables XIP
> prefetch at probe, plus the respective DT binding.
> 
> Testing:
> This series was tested on TI's
> AM62Ax SK with OSPI NAND flash and
> AM62Px SK with OSPI NOR flash:
> 
> Test log: https://gist.github.com/santhosh21/3ac2a0273065e86315a9b442327c9599
> Repo: https://github.com/santhosh21/linux/commits/fsas

Three versions within one day that's way too much. And b4 diff does not
work:

b4 diff 20260629072055.896322-1-s-k6@ti.com
Looking up https://lore.kernel.org/all/20260629072055.896322-1-s-k6@ti.com/
Grabbing thread from lore.kernel.org/all/20260629072055.896322-1-s-k6@ti.com/t.mbox.gz
Checking for older revisions
Grabbing search results from lore.kernel.org
  Added from v1: 6 patches
---
Analyzing 14 messages in the thread
WARNING: duplicate messages found at index 2
   Subject 1: memory: ti-k3-fsas: Add TI FSS_FSAS driver
   Subject 2: memory: ti-k3-fsas: Add TI FSS_FSAS driver
  2 is not a reply... assume additional patch
WARNING: duplicate messages found at index 1
   Subject 1: dt-bindings: memory: Add TI FSS_FSAS binding
   Subject 2: dt-bindings: memory: Add TI FSS_FSAS binding
  2 is not a reply... assume additional patch
Preparing fake-am for v1: dt-bindings: memory: Add TI FSS_FSAS binding
ERROR: v1 series incomplete; unable to create a fake-am range

If you want to make it difficult for maintainer to review, your patches
will be moved to the end of the queue.

Best regards,
Krzysztof