Messages in this thread |  | | From | Geert Uytterhoeven <> | | Date | Thu, 7 May 2026 14:44:20 +0200 | | Subject | Re: [PATCH 2/3] clk: renesas: r9a08g046: Add SSIF-2 clock and reset entries |
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On Tue, 5 May 2026 at 09:15, Biju <biju.das.au@gmail.com> wrote: > From: Biju Das <biju.das.jz@bp.renesas.com> > > Add SSIF-2 clock and reset entries in CPG driver. > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> i.e. will queue in renesas-clk for v7.2.
Gr{oetje,eeting}s,
Geert
-- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
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