Messages in this thread |  | | Date | Wed, 6 May 2026 21:43:44 +0200 | | From | Andrew Lunn <> | | Subject | Re: [PATCH net-next 09/12] gpio: tc956x: add TC956x/QPS615 support |
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> > ---------------------------------- > > | Host | > > ------+...+----------+........+--- > > |i2c| | PCIe | > > ----------------+...+----------+........+------ > > | TC956x |I2C| |upstream| | > > | ----- --+--------+--- | > > | ----- ------ ------- | PCIe switch | | > > | |SPI| |GPIO| |reset| | | | > > | ----- ------ |clock| | DS3 DS2 DS1 | | > > | ------- ---++--++--++-- | > > | ----- ------ downstream// \\ \\ | downstream > > | |MCU| |SRAM| /==========/ \\ \===== PCIe port 1 > > | ----- ------ //PCIe port 3 \\ | > > | || \======= downstream > > | ----+-----------++-----------+---- | PCIe port 2 > > | | M | internal PCIe endpoint | M | | > > | | S |------------------------| S | ------ | > > | | I | PCIe | | PCIe | I | |UART| | > > | | G |function 0| |function 1| G | ------ | > > | | E |----++----| |----++----| E | | > > | | N | eMAC 0 | | eMAC 1 | N | | > > --------+.......+------+.....+----------------- > > |USXGMII| |SGMII| > > --+.......+-- --+.....+-- > > | ARQ113C | | QEP8121 | > > | PHY | | PHY | > > ------------- ----------- > >
> Because the internal endpoint won't operate until the PCIe > power controller has enabled power, this GPIO driver and > the PCIe power control driver won't interfere with each > other's access to the shared registers.
What i find interesting is that there are two GPIOs, and two external downstream PCIe ports. A naive way of looking at this is that each external PCIe port has one GPIO. And the internal PCIe port does not have one. Hence the internal port might well work without any additional setup? That was my thinking.
But you are saying it is not as simple as this, and two GPIOs affect three ports? Do you have any idea what they actually do?
Andrew
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