Messages in this thread |  | | Date | Wed, 6 May 2026 20:45:38 +0530 | | Subject | Re: [PATCH v4 10/13] media: iris: Add power sequence for Glymur | | From | Vikash Garodia <> |
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On 5/5/2026 12:29 PM, Vishnu Reddy wrote: > Glymur has a secondary video codec core (vcodec1), equivalent to the > primary core (vcodec0), but with independent power domains, clocks, > and reset lines. Reuse the existing code wherever possible and add > power sequence for vcodec1. > > Signed-off-by: Vishnu Reddy <busanna.reddy@oss.qualcomm.com> > --- > .../platform/qcom/iris/iris_platform_common.h | 4 + > drivers/media/platform/qcom/iris/iris_vpu3x.c | 137 +++++++++++++++++++++ > drivers/media/platform/qcom/iris/iris_vpu_common.h | 1 + > .../platform/qcom/iris/iris_vpu_register_defines.h | 7 ++ > 4 files changed, 149 insertions(+) > > diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h > index 7d59e6364e9d..8995136ad29e 100644 > --- a/drivers/media/platform/qcom/iris/iris_platform_common.h > +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h > @@ -61,6 +61,9 @@ enum platform_clk_type { > IRIS_VPP0_HW_CLK, > IRIS_VPP1_HW_CLK, > IRIS_APV_HW_CLK, > + IRIS_AXI_VCODEC1_CLK, > + IRIS_VCODEC1_CLK, > + IRIS_VCODEC1_FREERUN_CLK, > }; > > struct platform_clk_data { > @@ -210,6 +213,7 @@ enum platform_pm_domain_type { > IRIS_VPP0_HW_POWER_DOMAIN, > IRIS_VPP1_HW_POWER_DOMAIN, > IRIS_APV_HW_POWER_DOMAIN, > + IRIS_VCODEC1_POWER_DOMAIN, > }; > > struct platform_pd_data { > diff --git a/drivers/media/platform/qcom/iris/iris_vpu3x.c b/drivers/media/platform/qcom/iris/iris_vpu3x.c > index 13fbb21c2182..0d0a239f9feb 100644 > --- a/drivers/media/platform/qcom/iris/iris_vpu3x.c > +++ b/drivers/media/platform/qcom/iris/iris_vpu3x.c > @@ -27,6 +27,16 @@ static bool iris_vpu3x_hw_power_collapsed(struct iris_core *core) > return pwr_status ? false : true; > } > > +static bool iris_vpu36_hw1_power_collapsed(struct iris_core *core) > +{ > + u32 value, pwr_status; > + > + value = readl(core->reg_base + WRAPPER_CORE_POWER_STATUS); > + pwr_status = value & BIT(4);
define these bits position
#define VCODEC0_POWER_STATUS BIT(1) #define VCODEC1_POWER_STATUS BIT(4)
with this,
Reviewed-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com>
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