Messages in this thread |  | | Date | Wed, 6 May 2026 15:56:21 +0100 | | From | Jonathan Cameron <> | | Subject | Re: [PATCH 07/10] m68k: mcf5441x: add CCR MISCCR2 bitfields |
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On Mon, 04 May 2026 19:16:45 +0200 Angelo Dureghello <angelo@kernel-space.org> wrote:
> From: Angelo Dureghello <adureghello@baylibre.com> > > Add CCR MISCCR2 register bitfields. > > Signed-off-by: Angelo Dureghello <adureghello@baylibre.com> https://sashiko.dev/#/patchset/20260504-wip-stmark2-dac-v1-0-874c36a4910d%40baylibre.com has valid suggestion that if you are using BIT() and GENMASK() you need a suitable header include.
> --- > arch/m68k/include/asm/m5441xsim.h | 15 +++++++++++++++ > 1 file changed, 15 insertions(+) > > diff --git a/arch/m68k/include/asm/m5441xsim.h b/arch/m68k/include/asm/m5441xsim.h > index 9ce2cbb05316..93f7943d5550 100644 > --- a/arch/m68k/include/asm/m5441xsim.h > +++ b/arch/m68k/include/asm/m5441xsim.h > @@ -145,6 +145,21 @@ > #define MCF_CCM_SBFCR 0xec090022 > #define MCF_CCM_FNACR 0xec090024 > > +/* Bit definitions and macros for MCF_CCM_MISCCR2 */ > +#define MCF_CCM_MISCCR2_ULPI BIT(0) > +#define MCF_CCM_MISCCR2_FB_HALF BIT(1) > +#define MCF_CCM_MISCCR2_ADC3_EN BIT(2) > +#define MCF_CCM_MISCCR2_ADC7_EN BIT(3) > +#define MCF_CCM_MISCCR2_ADC_EN BIT(4) > +#define MCF_CCM_MISCCR2_DAC0_SEL BIT(5) > +#define MCF_CCM_MISCCR2_DAC1_SEL BIT(6) > +#define MCF_CCM_MISCCR2_DCC_BYP BIT(7) > +#define MCF_CCM_MISCCR2_PLL_MODE GENMASK(9, 7) > +#define MCF_CCM_MISCCR2_SWT_SCR BIT(12) > +#define MCF_CCM_MISCCR2_RGPIO_HALF BIT(13) > +#define MCF_CCM_MISCCR2_DDR2_CLK BIT(14) > +#define MCF_CCM_MISCCR2_EXTCLK_BYP BIT(15) > + > /* > * UART module. > */ >
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