Messages in this thread Patch in this message |  | | From | Valentin Schneider <> | | Subject | [PATCH v9 08/10] x86/mm/pti: Introduce a kernel/user CR3 software signal | | Date | Tue, 5 May 2026 10:23:53 +0200 |
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Later commits will rely on being able to check whether a remote CPU is using the kernel or the user CR3.
This software signal needs to be updated before the actual CR3 write, IOW it always immediately precedes it:
KERNEL_CR3_LOADED := 1 SWITCH_TO_KERNEL_CR3 [...] KERNEL_CR3_LOADED := 0 SWITCH_TO_USER_CR3
The variable also gets mapped into the user space visible pages. I tried really hard not to do that, and at some point had something mostly working with having an alias to it through the cpu_entry_area accessed like so before the switch to the kernel CR3:
subq $10, %rsp sgdt (%rsp) movq 2(%rsp), \scratch_reg /* GDT address */ addq $10, %rsp
movl $1, CPU_ENTRY_AREA_kernel_cr3(\scratch_reg)
however this explodes when running 64-bit user code that invokes SYSCALL, since the scratch reg is %rsp itself, and I figured this was enough headaches.
This will only be really useful for NOHZ_FULL CPUs, but it should be cheaper to unconditionally update a never-used per-CPU variable living in its own cacheline than to check a shared cpumask such as housekeeping_cpumask(HK_TYPE_KERNEL_NOISE) at every entry.
Signed-off-by: Valentin Schneider <vschneid@redhat.com> --- arch/x86/Kconfig | 14 +++++++++++++ arch/x86/entry/calling.h | 18 +++++++++++++++++ arch/x86/entry/syscall_64.c | 4 ++++ arch/x86/include/asm/tlbflush.h | 3 +++ arch/x86/mm/pti.c | 36 ++++++++++++++++++++++----------- kernel/sched/isolation.c | 9 ++++++++- 6 files changed, 71 insertions(+), 13 deletions(-)
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 99bb5217649a8..36b4527ef69bd 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -2198,6 +2198,20 @@ config ADDRESS_MASKING The capability can be used for efficient address sanitizers (ASAN) implementation and for optimizations in JITs. +config TRACK_CR3 + def_bool n + prompt "Track which CR3 is in use" + depends on X86_64 && MITIGATION_PAGE_TABLE_ISOLATION && NO_HZ_FULL + help + This option adds a software signal that allows checking remotely + whether a CPU is using the user or the kernel page table. + + This allows further optimizations for NOHZ_FULL CPUs. + + This obviously makes the user<->kernel transition overhead even worse. + + If unsure, say N. + config HOTPLUG_CPU def_bool y depends on SMP diff --git a/arch/x86/entry/calling.h b/arch/x86/entry/calling.h index 77e2d920a6407..deb8224b5ee48 100644 --- a/arch/x86/entry/calling.h +++ b/arch/x86/entry/calling.h @@ -9,6 +9,7 @@ #include <asm/ptrace-abi.h> #include <asm/msr.h> #include <asm/nospec-branch.h> +#include <asm/jump_label.h> /* @@ -170,8 +171,22 @@ For 32-bit we have the following conventions - kernel is built with andq $(~PTI_USER_PGTABLE_AND_PCID_MASK), \reg .endm +.macro NOTE_CR3_SWITCH scratch_reg:req in_kernel:req +#ifdef CONFIG_TRACK_CR3 + STATIC_BRANCH_FALSE_LIKELY housekeeping_overridden, .Lend_\@ + LOCK_PREFIX +.if \in_kernel == 1 + orq $1, PER_CPU_VAR(kernel_cr3_loaded) +.else + andq $0, PER_CPU_VAR(kernel_cr3_loaded) +.endif +.Lend_\@: +#endif // CONFIG_TRACK_CR3 +.endm + .macro SWITCH_TO_KERNEL_CR3 scratch_reg:req ALTERNATIVE "jmp .Lend_\@", "", X86_FEATURE_PTI + NOTE_CR3_SWITCH \scratch_reg $1 mov %cr3, \scratch_reg ADJUST_KERNEL_CR3 \scratch_reg mov \scratch_reg, %cr3 @@ -182,6 +197,7 @@ For 32-bit we have the following conventions - kernel is built with PER_CPU_VAR(cpu_tlbstate + TLB_STATE_user_pcid_flush_mask) .macro SWITCH_TO_USER_CR3 scratch_reg:req scratch_reg2:req + NOTE_CR3_SWITCH \scratch_reg $0 mov %cr3, \scratch_reg ALTERNATIVE "jmp .Lwrcr3_\@", "", X86_FEATURE_PCID @@ -229,6 +245,7 @@ For 32-bit we have the following conventions - kernel is built with .macro SAVE_AND_SWITCH_TO_KERNEL_CR3 scratch_reg:req save_reg:req ALTERNATIVE "jmp .Ldone_\@", "", X86_FEATURE_PTI + NOTE_CR3_SWITCH \scratch_reg $1 movq %cr3, \scratch_reg movq \scratch_reg, \save_reg /* @@ -257,6 +274,7 @@ For 32-bit we have the following conventions - kernel is built with bt $PTI_USER_PGTABLE_BIT, \save_reg jnc .Lend_\@ + NOTE_CR3_SWITCH \scratch_reg $0 ALTERNATIVE "jmp .Lwrcr3_\@", "", X86_FEATURE_PCID /* diff --git a/arch/x86/entry/syscall_64.c b/arch/x86/entry/syscall_64.c index 71f032504e731..5d7596a86f240 100644 --- a/arch/x86/entry/syscall_64.c +++ b/arch/x86/entry/syscall_64.c @@ -83,6 +83,10 @@ static __always_inline bool do_syscall_x32(struct pt_regs *regs, int nr) return false; } +#ifdef CONFIG_TRACK_CR3 +DEFINE_PER_CPU_PAGE_ALIGNED(bool, kernel_cr3_loaded) = true; +#endif + /* Returns true to return using SYSRET, or false to use IRET */ __visible noinstr bool do_syscall_64(struct pt_regs *regs, int nr) { diff --git a/arch/x86/include/asm/tlbflush.h b/arch/x86/include/asm/tlbflush.h index 0545fe75c3fa1..0ec669eb0b4e7 100644 --- a/arch/x86/include/asm/tlbflush.h +++ b/arch/x86/include/asm/tlbflush.h @@ -17,6 +17,9 @@ #include <asm/pgtable.h> DECLARE_PER_CPU(u64, tlbstate_untag_mask); +#ifdef CONFIG_TRACK_CR3 +DECLARE_PER_CPU_PAGE_ALIGNED(bool, kernel_cr3_loaded); +#endif void __flush_tlb_all(void); diff --git a/arch/x86/mm/pti.c b/arch/x86/mm/pti.c index f7546e9e8e896..e75450cabd3a6 100644 --- a/arch/x86/mm/pti.c +++ b/arch/x86/mm/pti.c @@ -440,6 +440,18 @@ static void __init pti_clone_p4d(unsigned long addr) *user_p4d = *kernel_p4d; } +static void __init pti_clone_percpu(unsigned long va) +{ + phys_addr_t pa = per_cpu_ptr_to_phys((void *)va); + pte_t *target_pte; + + target_pte = pti_user_pagetable_walk_pte(va, false); + if (WARN_ON(!target_pte)) + return; + + *target_pte = pfn_pte(pa >> PAGE_SHIFT, PAGE_KERNEL); +} + /* * Clone the CPU_ENTRY_AREA and associated data into the user space visible * page table. @@ -450,25 +462,25 @@ static void __init pti_clone_user_shared(void) pti_clone_p4d(CPU_ENTRY_AREA_BASE); + /* + * This is done for all possible CPUs during boot to ensure that it's + * propagated to all mms. + */ for_each_possible_cpu(cpu) { /* * The SYSCALL64 entry code needs one word of scratch space * in which to spill a register. It lives in the sp2 slot * of the CPU's TSS. - * - * This is done for all possible CPUs during boot to ensure - * that it's propagated to all mms. */ + pti_clone_percpu((unsigned long)&per_cpu(cpu_tss_rw, cpu)); - unsigned long va = (unsigned long)&per_cpu(cpu_tss_rw, cpu); - phys_addr_t pa = per_cpu_ptr_to_phys((void *)va); - pte_t *target_pte; - - target_pte = pti_user_pagetable_walk_pte(va, false); - if (WARN_ON(!target_pte)) - return; - - *target_pte = pfn_pte(pa >> PAGE_SHIFT, PAGE_KERNEL); +#ifdef CONFIG_TRACK_CR3 + /* + * The entry code needs access to the @kernel_cr3_loaded percpu + * variable before the kernel CR3 is loaded. + */ + pti_clone_percpu((unsigned long)&per_cpu(kernel_cr3_loaded, cpu)); +#endif } } diff --git a/kernel/sched/isolation.c b/kernel/sched/isolation.c index ef152d401fe20..827e17760f1e2 100644 --- a/kernel/sched/isolation.c +++ b/kernel/sched/isolation.c @@ -18,7 +18,14 @@ enum hk_flags { HK_FLAG_KERNEL_NOISE = BIT(HK_TYPE_KERNEL_NOISE), }; -DEFINE_STATIC_KEY_FALSE(housekeeping_overridden); +/* + * This key is accessed in early entry code to drive the CPU isolation IPI + * deferral mechanism. This happens before a serializing instruction has been + * executed in the entry path. This is acceptable as a stale value will only be + * observed during transient CPU isolation states, and the updated value will be + * acted upon at the next kernel exit. + */ +DEFINE_STATIC_KEY_FALSE_ENTRY(housekeeping_overridden); EXPORT_SYMBOL_GPL(housekeeping_overridden); struct housekeeping { -- 2.52.0
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