Messages in this thread |  | | Date | Tue, 5 May 2026 19:20:35 +0200 | | Subject | Re: [PATCH 3/5] sched/fair: Prefer fully-idle SMT cores in asym-capacity idle selection | | From | Dietmar Eggemann <> |
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On 28.04.26 16:41, Andrea Righi wrote: > On systems with asymmetric CPU capacity (e.g., ACPI/CPPC reporting > different per-core frequencies), the wakeup path uses
I assume those CPPC systems w/ different per-core frequencies (like your Vera) are the only real one which would make use of this. Mobile big.LITTLE/DynamIQ don't have SMT.
Phil mentioned other machines (PowerPC ?) which had issues with using select_idle_capacity():
https://lore.kernel.org/r/20260325124840.GA98184@pauld.westford.csb
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> On an SMT system with asymmetric CPU capacities, SMT-aware idle > selection has been shown to improve throughput by around 15-18% for > CPU-bound workloads, running an amount of tasks equal to the amount of > SMT cores.
Just to make sure, this should be your internal NVBLAS benchmark. Is this 'ASYM (mainline) vs. ASYM + SMT' or 'NO_ASYM vs. ASYM + SMT' ? I try to match the cover letter's table numbers.
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> @@ -7997,8 +8013,9 @@ static int select_idle_cpu(struct task_struct *p, struct sched_domain *sd, bool > static int > select_idle_capacity(struct task_struct *p, struct sched_domain *sd, int target) > { > + bool prefers_idle_core = sched_smt_active() && test_idle_cores(target);
nit: why prefers_idle_core and not has_idle_core like in sis()?
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> @@ -8047,12 +8102,17 @@ static inline bool asym_fits_cpu(unsigned long util, > unsigned long util_max, > int cpu) > { > - if (sched_asym_cpucap_active()) > + if (sched_asym_cpucap_active()) { > /* > * Return true only if the cpu fully fits the task requirements > * which include the utilization and the performance hints. > + * > + * When SMT is active, also require that the core has no busy > + * siblings. > */ > - return (util_fits_cpu(util, util_min, util_max, cpu) > 0); > + return (!sched_smt_active() || is_core_idle(cpu)) && > + (util_fits_cpu(util, util_min, util_max, cpu) > 0); > + }
Not sure whether this has been discussed already. This makes all early bailout conditions in sis() idle core aware for 'ASYM + SMT' but it's not for 'NO_ASYM'?
Otherwise, LGTM.
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