Messages in this thread |  | | From | "Tian, Kevin" <> | | Subject | RE: [PATCH v2 1/1] vfio/nvgrace-gpu: Add Blackwell-Next GPU readiness check via CXL DVSEC | | Date | Fri, 10 Apr 2026 04:33:14 +0000 |
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> From: Alex Williamson <alex@shazbot.org> > Sent: Friday, April 10, 2026 2:31 AM > > On Thu, 9 Apr 2026 13:36:51 +0000 > Ankit Agrawal <ankita@nvidia.com> wrote: > > + > > + do { > > + pci_read_config_dword(pdev, > > + pcie_dvsec + > PCI_DVSEC_CXL_RANGE_SIZE_LOW(0), > > + &dvsec_memory_status); > > + > > + if (dvsec_memory_status & PCI_DVSEC_CXL_MEM_ACTIVE) > > + return 0; > > Do we need to monitor PCI_DVSEC_CXL_MEM_INFO_VALID in the loop too? >
is that bit static or dynamic? If static, better to check it one-off in probe instead of doing it in every wait.
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