Messages in this thread |  | | Date | Wed, 1 Apr 2026 18:07:27 +0530 | | Subject | Re: [PATCH v4 2/5] media: iris: Add hardware power on/off ops for X1P42100 | | From | Dikshita Agarwal <> |
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On 4/1/2026 3:54 PM, Wangao Wang wrote: > On X1P42100 the Iris block has an extra BSE clock. Wire this clock into > the power on/off sequence. > > The BSE clock is used to drive the Bin Stream Engine, which is a sub-block > of the video codec hardware responsible for bitstream-level processing. It > is required to be enabled separately from the core clock to ensure proper > codec operation. > > Signed-off-by: Wangao Wang <wangao.wang@oss.qualcomm.com> > --- > drivers/media/platform/qcom/iris/iris_vpu3x.c | 46 ++++++++++++++++++++++ > drivers/media/platform/qcom/iris/iris_vpu_common.h | 1 + > 2 files changed, 47 insertions(+) > > diff --git a/drivers/media/platform/qcom/iris/iris_vpu3x.c b/drivers/media/platform/qcom/iris/iris_vpu3x.c > index fe4423b951b1e9e31d06dffc69d18071cc985731..e6a62b3ca78efeefa2eed267636789a6b405689f 100644 > --- a/drivers/media/platform/qcom/iris/iris_vpu3x.c > +++ b/drivers/media/platform/qcom/iris/iris_vpu3x.c > @@ -71,6 +71,44 @@ static void iris_vpu3_power_off_hardware(struct iris_core *core) > iris_vpu_power_off_hw(core); > } > > +static int iris_vpu3_purwa_power_on_hw(struct iris_core *core) > +{ > + int ret; > + > + ret = iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]); > + if (ret) > + return ret; > + > + ret = iris_prepare_enable_clock(core, IRIS_HW_CLK); > + if (ret) > + goto err_disable_power; > + > + ret = iris_prepare_enable_clock(core, IRIS_BSE_HW_CLK); > + if (ret) > + goto err_disable_hw_clock; > + > + ret = dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN], true); > + if (ret) > + goto err_disable_bse_hw_clock; > + > + return 0; > + > +err_disable_bse_hw_clock: > + iris_disable_unprepare_clock(core, IRIS_BSE_HW_CLK); > +err_disable_hw_clock: > + iris_disable_unprepare_clock(core, IRIS_HW_CLK); > +err_disable_power: > + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]); > + > + return ret; > +} > + > +static void iris_vpu3_purwa_power_off_hardware(struct iris_core *core) > +{ > + iris_vpu3_power_off_hardware(core);
this will eventually call iris_vpu_power_off_hw which would try to disable IRIS_HW_AHB_CLK which is not applicable to purwa I think, will that not create any issue?
Other than this, change LGTM.
Thanks, Dikshita > + iris_disable_unprepare_clock(core, IRIS_BSE_HW_CLK); > +} > + > static void iris_vpu33_power_off_hardware(struct iris_core *core) > { > bool handshake_done = false, handshake_busy = false; > @@ -268,6 +306,14 @@ const struct vpu_ops iris_vpu3_ops = { > .calc_freq = iris_vpu3x_vpu4x_calculate_frequency, > }; > > +const struct vpu_ops iris_vpu3_purwa_ops = { > + .power_off_hw = iris_vpu3_purwa_power_off_hardware, > + .power_on_hw = iris_vpu3_purwa_power_on_hw, > + .power_off_controller = iris_vpu_power_off_controller, > + .power_on_controller = iris_vpu_power_on_controller, > + .calc_freq = iris_vpu3x_vpu4x_calculate_frequency, > +}; > + > const struct vpu_ops iris_vpu33_ops = { > .power_off_hw = iris_vpu33_power_off_hardware, > .power_on_hw = iris_vpu_power_on_hw, > diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.h b/drivers/media/platform/qcom/iris/iris_vpu_common.h > index f6dffc613b822341fb21e12de6b1395202f62cde..88a23cbdc06c5b38b4c8db67718cbd538f0e0721 100644 > --- a/drivers/media/platform/qcom/iris/iris_vpu_common.h > +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.h > @@ -10,6 +10,7 @@ struct iris_core; > > extern const struct vpu_ops iris_vpu2_ops; > extern const struct vpu_ops iris_vpu3_ops; > +extern const struct vpu_ops iris_vpu3_purwa_ops; > extern const struct vpu_ops iris_vpu33_ops; > extern const struct vpu_ops iris_vpu35_ops; > extern const struct vpu_ops iris_vpu4x_ops; >
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