Messages in this thread Patch in this message |  | | From | Aaron Kling via B4 Relay <> | | Date | Sat, 06 Sep 2025 15:16:52 -0500 | | Subject | [PATCH v3 2/9] dt-bindings: memory: tegra210: emc: Document OPP table and interconnect |
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From: Aaron Kling <webgeek1234@gmail.com>
These are needed for dynamic frequency scaling of the EMC controller.
Signed-off-by: Aaron Kling <webgeek1234@gmail.com> --- .../bindings/memory-controllers/nvidia,tegra210-emc.yaml | 11 +++++++++++ 1 file changed, 11 insertions(+)
diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-emc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-emc.yaml index bc8477e7ab193b7880bb681037985f3fccebf02f..4e4fb4acd7f9d376379a19b5f8e0256baaed5697 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-emc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-emc.yaml @@ -33,6 +33,9 @@ properties: items: - description: EMC general interrupt + "#interconnect-cells": + const: 0 + memory-region: maxItems: 1 description: @@ -44,6 +47,11 @@ properties: description: phandle of the memory controller node + operating-points-v2: + description: + Should contain freqs and voltages and opp-supported-hw property, which + is a bitfield indicating SoC speedo ID mask. + required: - compatible - reg @@ -79,4 +87,7 @@ examples: interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; memory-region = <&emc_table>; nvidia,memory-controller = <&mc>; + operating-points-v2 = <&dvfs_opp_table>; + + #interconnect-cells = <0>; }; -- 2.50.1
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