Messages in this thread |  | | From | Santhosh Kumar K <> | | Subject | [RFC PATCH 00/10] SPINAND PHY Tuning Series | | Date | Tue, 12 Aug 2025 01:02:09 +0530 |
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High-speed operation of certain SPI NAND/NOR controllers, such as the Cadence OSPI controller, requires execution of a PHY tuning sequence after switching the device to the appropriate mode (SDR or DDR). Without PHY, the controller in SDR mode can operate only at one-fourth of the reference clock. This series introduces an SDR-based PHY tuning procedure to enable higher-speed operation in SDR mode.
A new _execute_tuning() hook is added to the mtd_info structure for each MTD device. This hook is invoked when a flash partition named 'ospi.phypattern' is detected. The flash-specific _execute_tuning() implementation retrieves the PHY tuning parameters-such as the pre-defined tuning pattern and its size-and uses them to perform a readback/compare operation against the known pre-flashed data in 'ospi.phypattern' as part of the tuning process.
From the flash driver, spi_mem_execute_tuning() is called with an appropriate read_op. This function invokes cqspi_execute_tuning(), which contains the PHY tuning algorithm. These APIs are flash-agnostic, relying only on the correct read_op being passed. DDR mode tuning with DQS support will be implemented in a future series.
In the NOR driver, _execute_tuning() follows the same approach of pre-flashing a known pattern into the target partition and reading it back during tuning. For NAND flashes, the tuning pattern can be written directly to the cache via write_to_cache() and subsequently read back using read_from_cache() during the tuning procedure. This support will be added in a later phase.
At present, the series does not implement fallback handling for tuning failures (e.g., reducing maximum frequency or adjusting dummy cycles). Future enhancements will add fallback mechanisms to select a lower operating frequency and optimal dummy cycle configuration.
Device Tree updates required for this functionality will be submitted in a separate patch series after this one is merged.
This series was tested on TI's AM62A SK with W35N01JW OSPI NAND flash. The read and write throughput with and without PHY:
Without PHY: READ: 7.1 MB/s WRITE: 6 MB/s
Wth PHY: READ: 35.1 MB/s WRITE: 9.2 MB/s
Repo: https://github.com/santhosh21/linux/commits/spinand_phy_rfc_v1 Test log: https://gist.github.com/santhosh21/d2d52cc03d2423200971b0ab9c3b9365
Signed-off-by: Santhosh Kumar K <s-k6@ti.com>
Pratyush Yadav (2): spi: spi-mem: Introduce support for tuning controller spi: cadence-quadspi: Enable PHY for aligned DAC reads
Santhosh Kumar K (8): spi: spi-mem: Define spi_mem_tuning_params and spi_mem_get_tuning_params() mtd: nand: spi: Introduce _execute_tuning for mtd devices mtd: mtdcore: Call mtd_execute_tuning during mtd_register spi: cadence-quadspi: Move cqspi_readdata_capture() above all operations spi: cadence-quadspi: Use BIT() macro for CQSPI_REG_READCAPTURE_BYPASS spi: cadence-quadspi: Enable PHY for data writes spi: cadence-quadspi: Implement PHY for higher frequencies in SDR mode spi: cadence-quadspi: Define cqspi_get_tuning_params()
drivers/mtd/mtdcore.c | 19 + drivers/mtd/mtdcore.h | 1 + drivers/mtd/nand/spi/core.c | 61 +++ drivers/spi/spi-cadence-quadspi.c | 727 ++++++++++++++++++++++++++++-- drivers/spi/spi-mem.c | 22 + include/linux/mtd/mtd.h | 1 + include/linux/spi/spi-mem.h | 23 + 7 files changed, 823 insertions(+), 31 deletions(-)
-- 2.34.1
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