Messages in this thread |  | | Date | Fri, 18 Jul 2025 16:08:58 +0200 | | Subject | Re: [PATCH V3 5/5] raid6: test: Add support for RISC-V | | From | Alexandre Ghiti <> |
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Hi Chunyan,
On 7/18/25 09:27, Chunyan Zhang wrote: > From: Chunyan Zhang <zhang.lyra@gmail.com> > > Add RISC-V code to be compiled to allow the userspace raid6test program > to be built and run on RISC-V. > > Signed-off-by: Chunyan Zhang <zhang.lyra@gmail.com> > --- > lib/raid6/test/Makefile | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/lib/raid6/test/Makefile b/lib/raid6/test/Makefile > index 8f2dd2210ba8..09bbe2b14cce 100644 > --- a/lib/raid6/test/Makefile > +++ b/lib/raid6/test/Makefile > @@ -35,6 +35,11 @@ ifeq ($(ARCH),aarch64) > HAS_NEON = yes > endif > > +ifeq ($(findstring riscv,$(ARCH)),riscv) > + CFLAGS += -I../../../arch/riscv/include -DCONFIG_RISCV=1 > + HAS_RVV = yes > +endif > + > ifeq ($(findstring ppc,$(ARCH)),ppc) > CFLAGS += -I../../../arch/powerpc/include > HAS_ALTIVEC := $(shell printf '$(pound)include <altivec.h>\nvector int a;\n' |\ > @@ -63,6 +68,9 @@ else ifeq ($(HAS_ALTIVEC),yes) > vpermxor1.o vpermxor2.o vpermxor4.o vpermxor8.o > else ifeq ($(ARCH),loongarch64) > OBJS += loongarch_simd.o recov_loongarch_simd.o > +else ifeq ($(HAS_RVV),yes) > + OBJS += rvv.o recov_rvv.o > + CFLAGS += -DCONFIG_RISCV_ISA_V=1 > endif > > .c.o:
Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com> Tested-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Thanks for the new version, I'll take that for 6.17,
Alex
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