Messages in this thread |  | | From | Geert Uytterhoeven <> | | Date | Thu, 22 May 2025 10:50:33 +0200 | | Subject | Re: [PATCH 4/5] clk: renesas: r9a09g056: Add clock and reset entries for WDT controllers |
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On Tue, 13 May 2025 at 17:46, Prabhakar <prabhakar.csengg@gmail.com> wrote: > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > Add module clock and reset definitions for WDT0-3, which are available > on the RZ/V2N (R9A09G056) SoC. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> i.e. will queue in renesas-clk for v6.17.
Gr{oetje,eeting}s,
Geert
-- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
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