Messages in this thread Patch in this message |  | | From | Melody Olvera <> | | Date | Mon, 14 Apr 2025 16:21:53 -0700 | | Subject | [PATCH v4 4/4] arm64: dts: qcom: sm8750: Add LLCC node |
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Add LLCC node for SM8750 SoC.
Signed-off-by: Melody Olvera <melody.olvera@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> --- arch/arm64/boot/dts/qcom/sm8750.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi index 612b99dc3c55495d06b3577531ec6996554bbbb6..5d3a96c6412095fd89ab1fd9a586fe9ad4dd7ee9 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -3310,6 +3310,24 @@ gem_noc: interconnect@24100000 { #interconnect-cells = <2>; }; + system-cache-controller@24800000 { + compatible = "qcom,sm8750-llcc"; + reg = <0x0 0x24800000 0x0 0x200000>, + <0x0 0x25800000 0x0 0x200000>, + <0x0 0x24c00000 0x0 0x200000>, + <0x0 0x25c00000 0x0 0x200000>, + <0x0 0x26800000 0x0 0x200000>, + <0x0 0x26c00000 0x0 0x200000>; + reg-names = "llcc0_base", + "llcc1_base", + "llcc2_base", + "llcc3_base", + "llcc_broadcast_base", + "llcc_broadcast_and_base"; + + interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; + }; + nsp_noc: interconnect@320c0000 { compatible = "qcom,sm8750-nsp-noc"; reg = <0x0 0x320c0000 0x0 0x13080>; -- 2.48.1
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