Messages in this thread |  | | Date | Mon, 10 Feb 2025 10:47:58 +0800 | | Subject | Re: [PATCH net-next v3 01/14] dt-bindings: net: Add PPE for Qualcomm IPQ9574 SoC | | From | Jie Gan <> |
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On 2/9/2025 10:29 PM, Luo Jie wrote: > The PPE (packet process engine) hardware block is available in Qualcomm > IPQ chipsets that support PPE architecture, such as IPQ9574. The PPE in > the IPQ9574 SoC includes six ethernet ports (6 GMAC and 6 XGMAC), which > are used to connect with external PHY devices by PCS. It includes an L2 > switch function for bridging packets among the 6 ethernet ports and the > CPU port. The CPU port enables packet transfer between the ethernet > ports and the ARM cores in the SoC, using the ethernet DMA. > > The PPE also includes packet processing offload capabilities for various > networking functions such as route and bridge flows, VLANs, different > tunnel protocols and VPN. > > Signed-off-by: Luo Jie <quic_luoj@quicinc.com> > --- > .../devicetree/bindings/net/qcom,ipq9574-ppe.yaml | 406 +++++++++++++++++++++ > 1 file changed, 406 insertions(+) > > diff --git a/Documentation/devicetree/bindings/net/qcom,ipq9574-ppe.yaml b/Documentation/devicetree/bindings/net/qcom,ipq9574-ppe.yaml > new file mode 100644 > index 000000000000..be6f9311eebb > --- /dev/null > +++ b/Documentation/devicetree/bindings/net/qcom,ipq9574-ppe.yaml > @@ -0,0 +1,406 @@ > +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/net/qcom,ipq9574-ppe.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm IPQ packet process engine (PPE) > + > +maintainers: > + - Luo Jie <quic_luoj@quicinc.com> > + - Lei Wei <quic_leiwei@quicinc.com> > + - Suruchi Agarwal <quic_suruchia@quicinc.com> > + - Pavithra R <quic_pavir@quicinc.com>> > + > +description: You have multiple paragrahs here. description: -> description: |
Thanks, Jie
> + The Ethernet functionality in the PPE (Packet Process Engine) is comprised > + of three components, the switch core, port wrapper and Ethernet DMA. > + > + The Switch core in the IPQ9574 PPE has maximum of 6 front panel ports and > + two FIFO interfaces. One of the two FIFO interfaces is used for Ethernet > + port to host CPU communication using Ethernet DMA. The other is used > + communicating to the EIP engine which is used for IPsec offload. On the > + IPQ9574, the PPE includes 6 GMAC/XGMACs that can be connected with external > + Ethernet PHY. Switch core also includes BM (Buffer Management), QM (Queue > + Management) and SCH (Scheduler) modules for supporting the packet processing. > + > + The port wrapper provides connections from the 6 GMAC/XGMACS to UNIPHY (PCS) > + supporting various modes such as SGMII/QSGMII/PSGMII/USXGMII/10G-BASER. There > + are 3 UNIPHY (PCS) instances supported on the IPQ9574. > + > + Ethernet DMA is used to transmit and receive packets between the six Ethernet > + ports and ARM host CPU. > + > + The follow diagram shows the PPE hardware block along with its connectivity > + to the external hardware blocks such clock hardware blocks (CMNPLL, GCC, > + NSS clock controller) and ethernet PCS/PHY blocks. For depicting the PHY > + connectivity, one 4x1 Gbps PHY (QCA8075) and two 10 GBps PHYs are used as an > + example. > + - | > + +---------+ > + | 48 MHZ | > + +----+----+ > + |(clock) > + v > + +----+----+ > + +------| CMN PLL | > + | +----+----+ > + | |(clock) > + | v > + | +----+----+ +----+----+ (clock) +----+----+ > + | +---| NSSCC | | GCC |--------->| MDIO | > + | | +----+----+ +----+----+ +----+----+ > + | | |(clock & reset) |(clock) > + | | v v > + | | +-----------------------------+----------+----------+---------+ > + | | | +-----+ |EDMA FIFO | | EIP FIFO| > + | | | | SCH | +----------+ +---------+ > + | | | +-----+ | | | > + | | | +------+ +------+ +-------------------+ | > + | | | | BM | | QM | IPQ9574-PPE | L2/L3 Process | | > + | | | +------+ +------+ +-------------------+ | > + | | | | | > + | | | +-------+ +-------+ +-------+ +-------+ +-------+ +-------+ | > + | | | | MAC0 | | MAC1 | | MAC2 | | MAC3 | | XGMAC4| |XGMAC5 | | > + | | | +---+---+ +---+---+ +---+---+ +---+---+ +---+---+ +---+---+ | > + | | | | | | | | | | > + | | +-----+---------+---------+---------+---------+---------+-----+ > + | | | | | | | | > + | | +---+---------+---------+---------+---+ +---+---+ +---+---+ > + +--+---->| PCS0 | | PCS1 | | PCS2 | > + |(clock) +---+---------+---------+---------+---+ +---+---+ +---+---+ > + | | | | | | | > + | +---+---------+---------+---------+---+ +---+---+ +---+---+ > + +------->| QCA8075 PHY | | PHY4 | | PHY5 | > + (clock) +-------------------------------------+ +-------+ +-------+ > + > +properties: > + compatible: > + enum: > + - qcom,ipq9574-ppe > + > + reg: > + maxItems: 1 > + > + clocks: > + items: > + - description: PPE core clock from NSS clock controller > + - description: PPE APB (Advanced Peripheral Bus) clock from NSS clock controller > + - description: PPE ingress process engine clock from NSS clock controller > + - description: PPE BM, QM and scheduler clock from NSS clock controller > + > + clock-names: > + items: > + - const: ppe > + - const: apb > + - const: ipe > + - const: btq > + > + resets: > + maxItems: 1 > + description: PPE reset, which is necessary before configuring PPE hardware > + > + interconnects: > + items: > + - description: Clock path leading to PPE switch core function > + - description: Clock path leading to PPE register access > + - description: Clock path leading to QoS generation > + - description: Clock path leading to timeout reference > + - description: Clock path leading to NSS NOC from memory NOC > + - description: Clock path leading to memory NOC from NSS NOC > + - description: Clock path leading to enhanced memory NOC from NSS NOC > + > + interconnect-names: > + items: > + - const: ppe > + - const: ppe_cfg > + - const: qos_gen > + - const: timeout_ref > + - const: nssnoc_memnoc > + - const: memnoc_nssnoc > + - const: memnoc_nssnoc_1 > + > + ethernet-dma: > + type: object > + additionalProperties: false > + description: > + EDMA (Ethernet DMA) is used to transmit packets between PPE and ARM > + host CPU. There are 32 TX descriptor rings, 32 TX completion rings, > + 24 RX descriptor rings and 8 RX fill rings supported. > + > + properties: > + clocks: > + items: > + - description: EDMA system clock from NSS Clock Controller > + - description: EDMA APB (Advanced Peripheral Bus) clock from > + NSS Clock Controller > + > + clock-names: > + items: > + - const: sys > + - const: apb > + > + resets: > + maxItems: 1 > + description: EDMA reset from NSS clock controller > + > + interrupts: > + minItems: 29 > + maxItems: 57 > + > + interrupt-names: > + minItems: 29 > + maxItems: 57 > + items: > + pattern: '^(txcmpl_([0-9]|[1-2][0-9]|3[0-1])|rxdesc_([0-9]|1[0-9]|2[0-3])|misc)$' > + description: > + Interrupts "txcmpl_[0-31]" are the Ethernet DMA Tx completion ring interrupts. > + Interrupts "rxdesc_[0-23]" are the Ethernet DMA Rx Descriptor ring interrupts. > + Interrupt "misc" is the Ethernet DMA miscellaneous error interrupt. > + > + required: > + - clocks > + - clock-names > + - resets > + - interrupts > + - interrupt-names > + > +required: > + - compatible > + - reg > + - clocks > + - clock-names > + - resets > + - interconnects > + - interconnect-names > + - ethernet-dma > + > +allOf: > + - $ref: ethernet-switch.yaml > + > +unevaluatedProperties: false > + > +examples: > + - | > + #include <dt-bindings/clock/qcom,ipq9574-gcc.h> > + #include <dt-bindings/interconnect/qcom,ipq9574.h> > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + > + ethernet-switch@3a000000 { > + compatible = "qcom,ipq9574-ppe"; > + reg = <0x3a000000 0xbef800>; > + clocks = <&nsscc 80>, > + <&nsscc 79>, > + <&nsscc 81>, > + <&nsscc 78>; > + clock-names = "ppe", > + "apb", > + "ipe", > + "btq"; > + resets = <&nsscc 108>; > + interconnects = <&nsscc MASTER_NSSNOC_PPE &nsscc SLAVE_NSSNOC_PPE>, > + <&nsscc MASTER_NSSNOC_PPE_CFG &nsscc SLAVE_NSSNOC_PPE_CFG>, > + <&gcc MASTER_NSSNOC_QOSGEN_REF &gcc SLAVE_NSSNOC_QOSGEN_REF>, > + <&gcc MASTER_NSSNOC_TIMEOUT_REF &gcc SLAVE_NSSNOC_TIMEOUT_REF>, > + <&gcc MASTER_MEM_NOC_NSSNOC &gcc SLAVE_MEM_NOC_NSSNOC>, > + <&gcc MASTER_NSSNOC_MEMNOC &gcc SLAVE_NSSNOC_MEMNOC>, > + <&gcc MASTER_NSSNOC_MEM_NOC_1 &gcc SLAVE_NSSNOC_MEM_NOC_1>; > + interconnect-names = "ppe", > + "ppe_cfg", > + "qos_gen", > + "timeout_ref", > + "nssnoc_memnoc", > + "memnoc_nssnoc", > + "memnoc_nssnoc_1"; > + > + ethernet-dma { > + clocks = <&nsscc 77>, > + <&nsscc 76>; > + clock-names = "sys", > + "apb"; > + resets = <&nsscc 0>; > + interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 504 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "txcmpl_8", > + "txcmpl_9", > + "txcmpl_10", > + "txcmpl_11", > + "txcmpl_12", > + "txcmpl_13", > + "txcmpl_14", > + "txcmpl_15", > + "txcmpl_16", > + "txcmpl_17", > + "txcmpl_18", > + "txcmpl_19", > + "txcmpl_20", > + "txcmpl_21", > + "txcmpl_22", > + "txcmpl_23", > + "txcmpl_24", > + "txcmpl_25", > + "txcmpl_26", > + "txcmpl_27", > + "txcmpl_28", > + "txcmpl_29", > + "txcmpl_30", > + "txcmpl_31", > + "rxdesc_20", > + "rxdesc_21", > + "rxdesc_22", > + "rxdesc_23", > + "misc"; > + }; > + > + ethernet-ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@1 { > + reg = <1>; > + phy-mode = "qsgmii"; > + managed = "in-band-status"; > + phy-handle = <&phy0>; > + pcs-handle = <&pcs0_mii0>; > + clocks = <&nsscc 33>, > + <&nsscc 34>, > + <&nsscc 37>; > + clock-names = "mac", > + "rx", > + "tx"; > + resets = <&nsscc 29>, > + <&nsscc 96>, > + <&nsscc 97>; > + reset-names = "mac", > + "rx", > + "tx"; > + }; > + > + port@2 { > + reg = <2>; > + phy-mode = "qsgmii"; > + managed = "in-band-status"; > + phy-handle = <&phy1>; > + pcs-handle = <&pcs0_mii1>; > + clocks = <&nsscc 40>, > + <&nsscc 41>, > + <&nsscc 44>; > + clock-names = "mac", > + "rx", > + "tx"; > + resets = <&nsscc 30>, > + <&nsscc 98>, > + <&nsscc 99>; > + reset-names = "mac", > + "rx", > + "tx"; > + }; > + > + port@3 { > + reg = <3>; > + phy-mode = "qsgmii"; > + managed = "in-band-status"; > + phy-handle = <&phy2>; > + pcs-handle = <&pcs0_mii2>; > + clocks = <&nsscc 47>, > + <&nsscc 48>, > + <&nsscc 51>; > + clock-names = "mac", > + "rx", > + "tx"; > + resets = <&nsscc 31>, > + <&nsscc 100>, > + <&nsscc 101>; > + reset-names = "mac", > + "rx", > + "tx"; > + }; > + > + port@4 { > + reg = <4>; > + phy-mode = "qsgmii"; > + managed = "in-band-status"; > + phy-handle = <&phy3>; > + pcs-handle = <&pcs0_mii3>; > + clocks = <&nsscc 54>, > + <&nsscc 55>, > + <&nsscc 58>; > + clock-names = "mac", > + "rx", > + "tx"; > + resets = <&nsscc 32>, > + <&nsscc 102>, > + <&nsscc 103>; > + reset-names = "mac", > + "rx", > + "tx"; > + }; > + > + port@5 { > + reg = <5>; > + phy-mode = "usxgmii"; > + managed = "in-band-status"; > + phy-handle = <&phy4>; > + pcs-handle = <&pcs1_mii0>; > + clocks = <&nsscc 61>, > + <&nsscc 62>, > + <&nsscc 65>; > + clock-names = "mac", > + "rx", > + "tx"; > + resets = <&nsscc 33>, > + <&nsscc 104>, > + <&nsscc 105>; > + reset-names = "mac", > + "rx", > + "tx"; > + }; > + > + port@6 { > + reg = <6>; > + phy-mode = "usxgmii"; > + managed = "in-band-status"; > + phy-handle = <&phy5>; > + pcs-handle = <&pcs2_mii0>; > + clocks = <&nsscc 68>, > + <&nsscc 69>, > + <&nsscc 72>; > + clock-names = "mac", > + "rx", > + "tx"; > + resets = <&nsscc 34>, > + <&nsscc 106>, > + <&nsscc 107>; > + reset-names = "mac", > + "rx", > + "tx"; > + }; > + }; > + }; >
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