Messages in this thread |  | | Date | Tue, 2 Dec 2025 22:06:24 +0530 | | Subject | Re: [PATCH v10 1/3] firmware: qcom_scm: Add API to get waitqueue IRQ info | | From | Shivendra Pratap <> |
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On 12/2/2025 5:13 PM, Mukesh Ojha wrote: > On Sun, Nov 30, 2025 at 08:11:02PM +0530, Shivendra Pratap wrote: >> From: Unnathi Chalicheemala <unnathi.chalicheemala@oss.qualcomm.com> >>
[SNIP..]
>> >> diff --git a/drivers/firmware/qcom/qcom_scm.c b/drivers/firmware/qcom/qcom_scm.c >> index e777b7cb9b127944fe112f453cae9cbc40c06cae..79ab1707f71b0157835deaea6309f33016e3de8c 100644 >> --- a/drivers/firmware/qcom/qcom_scm.c >> +++ b/drivers/firmware/qcom/qcom_scm.c >> @@ -29,12 +29,18 @@ >> #include <linux/reset-controller.h> >> #include <linux/sizes.h> >> #include <linux/types.h> >> +#include <dt-bindings/interrupt-controller/arm-gic.h> > > At most places, where this header is used there is a line feed > before it, if the header before it is not from dt-bindings.
Ack.
> >> >> #include "qcom_scm.h" >> #include "qcom_tzmem.h" >> >> static u32 download_mode; >> >> +#define GIC_SPI_BASE 32 >> +#define GIC_MAX_SPI 1019 // SPIs in GICv3 spec range from 32..1019 >> +#define GIC_ESPI_BASE 4096 >> +#define GIC_MAX_ESPI 5119 // ESPIs in GICv3 spec range from 4096..5119 >> + >> struct qcom_scm { >> struct device *dev; >> struct clk *core_clk; >> @@ -2223,6 +2229,55 @@ bool qcom_scm_is_available(void) >> } >> EXPORT_SYMBOL_GPL(qcom_scm_is_available); >> >> +static int qcom_scm_fill_irq_fwspec_params(struct irq_fwspec *fwspec, u32 hwirq) >> +{ >> + if (hwirq >= GIC_SPI_BASE && hwirq <= GIC_MAX_SPI) { >> + fwspec->param[0] = GIC_SPI; >> + fwspec->param[1] = hwirq - GIC_SPI_BASE; >> + } else if (hwirq >= GIC_ESPI_BASE && hwirq <= GIC_MAX_ESPI) { >> + fwspec->param[0] = GIC_ESPI; >> + fwspec->param[1] = hwirq - GIC_ESPI_BASE; >> + } else { >> + WARN(1, "Unexpected hwirq: %d\n", hwirq); >> + return -ENXIO; >> + } > > line feed after } would make it look better..
Ack.
> >> + fwspec->param[2] = IRQ_TYPE_EDGE_RISING; >> + fwspec->param_count = 3; >> + >> + return 0; >> +} >> + >> +static int qcom_scm_get_waitq_irq(struct qcom_scm *scm) >> +{ >> + struct device_node *parent_irq_node; > > after desc ?
ok.
> >> + struct qcom_scm_desc desc = { >> + .svc = QCOM_SCM_SVC_WAITQ, >> + .cmd = QCOM_SCM_WAITQ_GET_INFO, >> + .owner = ARM_SMCCC_OWNER_SIP >> + }; >> + struct irq_fwspec fwspec; >> + struct qcom_scm_res res; >> + u32 hwirq; >> + int ret; >> + >> + ret = qcom_scm_call_atomic(scm->dev, &desc, &res); >> + if (ret) >> + return ret; >> + >> + hwirq = res.result[1] & GENMASK(15, 0); >> + > > redundant line feed ?
will remove. thanks.
> >> + ret = qcom_scm_fill_irq_fwspec_params(&fwspec, hwirq); >> + if (ret) >> + return ret; > > Line feed needed here after return or } ?
will add it.
thanks, Shivendra
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