Messages in this thread |  | | Date | Wed, 15 Jan 2025 14:01:10 -0800 | | Subject | Re: [PATCH 01/35] drm/msm/dpu: skip watchdog timer programming through TOP on >= SM8450 | | From | Abhinav Kumar <> |
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On 12/13/2024 2:14 PM, Dmitry Baryshkov wrote: > The SM8450 and later chips have DPU_MDP_PERIPH_0_REMOVED feature bit > set, which means that those platforms have dropped some of the > registers, including the WD TIMER-related ones. Stop providing the > callback to program WD timer on those platforms. > > Fixes: 100d7ef6995d ("drm/msm/dpu: add support for SM8450") > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c > index ad19330de61abd66762671cf253276695b303b32..562a3f4c5238a3ad6c8c1fa4d285b9165ada3cfd 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c > @@ -272,7 +272,7 @@ static void _setup_mdp_ops(struct dpu_hw_mdp_ops *ops, > > if (cap & BIT(DPU_MDP_VSYNC_SEL)) > ops->setup_vsync_source = dpu_hw_setup_vsync_sel; > - else > + else if (!(cap & BIT(DPU_MDP_PERIPH_0_REMOVED))) > ops->setup_vsync_source = dpu_hw_setup_wd_timer; > > ops->get_safe_status = dpu_hw_get_safe_status;
Yes, this has also moved to INTF starting sm8450.
Note : wd timer programming in interface is missing, so that support needs to be added as well
For this change,
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
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