Messages in this thread | ![/](/images/icornerl.gif) | | Subject | Re: [PATCH v10 1/2] x86/mm: Don't disable PCID if "incomplete Global INVLPG flushes" is fixed by microcode | From | Xi Ruoyao <> | Date | Wed, 26 Jun 2024 21:10:01 +0800 |
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Ping.
Ok to queue these two into some branch for integration?
On Wed, 2024-05-22 at 10:06 +0800, Xi Ruoyao wrote: > Per the "Processor Specification Update" documentations referred by the > intel-microcode-20240312 release note, this microcode release has fixed > the issue for all affected models. > > So don't disable PCID if the microcode is new enough. The precise > minimum microcode revision fixing the issue is provided by engineer from > Intel. > > Cc: Dave Hansen <dave.hansen@linux.intel.com> > Cc: Michael Kelley <mhklinux@outlook.com> > Cc: Pawan Gupta <pawan.kumar.gupta@linux.intel.com> > Cc: Sean Christopherson <seanjc@google.com> > Cc: Andrew Cooper <andrew.cooper3@citrix.com> > Link: https://lore.kernel.org/all/168436059559.404.13934972543631851306.tip-bot2@tip-bot2/ > Link: https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/releases/tag/microcode-20240312 > Link: https://cdrdv2.intel.com/v1/dl/getContent/740518 # RPL042, rev. 13 > Link: https://cdrdv2.intel.com/v1/dl/getContent/682436 # ADL063, rev. 24 > Link: https://lore.kernel.org/all/20240325231300.qrltbzf6twm43ftb@desk/ > Signed-off-by: Xi Ruoyao <xry111@xry111.site> > --- > arch/x86/mm/init.c | 22 ++++++++++++++-------- > 1 file changed, 14 insertions(+), 8 deletions(-) > > diff --git a/arch/x86/mm/init.c b/arch/x86/mm/init.c > index eb503f53c319..e960196e8058 100644 > --- a/arch/x86/mm/init.c > +++ b/arch/x86/mm/init.c > @@ -264,27 +264,33 @@ static void __init probe_page_size_mask(void) > > /* > * INVLPG may not properly flush Global entries > - * on these CPUs when PCIDs are enabled. > + * on these CPUs when PCIDs are enabled and the > + * microcode is not updated to fix the issue. > */ > static const struct x86_cpu_id invlpg_miss_ids[] = { > - X86_MATCH_VFM(INTEL_ALDERLAKE, 0), > - X86_MATCH_VFM(INTEL_ALDERLAKE_L, 0), > - X86_MATCH_VFM(INTEL_ATOM_GRACEMONT, 0), > - X86_MATCH_VFM(INTEL_RAPTORLAKE, 0), > - X86_MATCH_VFM(INTEL_RAPTORLAKE_P, 0), > - X86_MATCH_VFM(INTEL_RAPTORLAKE_S, 0), > + X86_MATCH_VFM(INTEL_ALDERLAKE, 0x2e), > + X86_MATCH_VFM(INTEL_ALDERLAKE_L, 0x42c), > + X86_MATCH_VFM(INTEL_ATOM_GRACEMONT, 0x11), > + X86_MATCH_VFM(INTEL_RAPTORLAKE, 0x118), > + X86_MATCH_VFM(INTEL_RAPTORLAKE_P, 0x4117), > + X86_MATCH_VFM(INTEL_RAPTORLAKE_S, 0x2e), > {} > }; > > static void setup_pcid(void) > { > + const struct x86_cpu_id *invlpg_miss_match; > + > if (!IS_ENABLED(CONFIG_X86_64)) > return; > > if (!boot_cpu_has(X86_FEATURE_PCID)) > return; > > - if (x86_match_cpu(invlpg_miss_ids)) { > + invlpg_miss_match = x86_match_cpu(invlpg_miss_ids); > + > + if (invlpg_miss_match && > + boot_cpu_data.microcode < invlpg_miss_match->driver_data) { > pr_info("Incomplete global flushes, disabling PCID"); > setup_clear_cpu_cap(X86_FEATURE_PCID); > return;
-- Xi Ruoyao <xry111@xry111.site> School of Aerospace Science and Technology, Xidian University
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