Messages in this thread Patch in this message | ![/](/images/icornerl.gif) | | From | "Peng Fan (OSS)" <> | Date | Sat, 04 May 2024 08:48:56 +0800 | Subject | [PATCH 03/18] clk: imx: composite-7ulp: Check the PCC present bit |
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From: Ye Li <ye.li@nxp.com>
When some module is disabled by fuse, its PCC PR bit is default 0 and PCC is not operational. Any write to this PCC will cause SError.
Fixes: b40ba8065347 ("clk: imx: Update the compsite driver to support imx8ulp") Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> --- drivers/clk/imx/clk-composite-7ulp.c | 5 +++++ 1 file changed, 5 insertions(+)
diff --git a/drivers/clk/imx/clk-composite-7ulp.c b/drivers/clk/imx/clk-composite-7ulp.c index e208ddc51133..e70a03e7299c 100644 --- a/drivers/clk/imx/clk-composite-7ulp.c +++ b/drivers/clk/imx/clk-composite-7ulp.c @@ -14,6 +14,7 @@ #include "../clk-fractional-divider.h" #include "clk.h" +#define PCG_PR_MASK BIT(31) #define PCG_PCS_SHIFT 24 #define PCG_PCS_MASK 0x7 #define PCG_CGC_SHIFT 30 @@ -78,6 +79,10 @@ static struct clk_hw *imx_ulp_clk_hw_composite(const char *name, struct clk_hw *hw; u32 val; + val = readl(reg); + if (!(val & PCG_PR_MASK)) + return ERR_PTR(-ENODEV); + if (mux_present) { mux = kzalloc(sizeof(*mux), GFP_KERNEL); if (!mux) -- 2.37.1
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