Messages in this thread Patch in this message | ![/](/images/icornerl.gif) | | From | Yangyu Chen <> | Subject | [PATCH 1/2] docs: riscv: Clarify risc-v hwprobe RISCV_HWPROBE_MISALIGNED_* docs. | Date | Sun, 19 May 2024 00:00:11 +0800 |
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From: enh <enh@google.com>
These only tell you about scalar accesses, not vector accesses.
Signed-off-by: Elliott Hughes <enh@google.com> Reviewed-by: Charlie Jenkins <charlie@rivosinc.com> Signed-off-by: Yangyu Chen <cyy@cyyself.name> --- Documentation/arch/riscv/hwprobe.rst | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst index b2bcc9eed9aa..239be63f5089 100644 --- a/Documentation/arch/riscv/hwprobe.rst +++ b/Documentation/arch/riscv/hwprobe.rst @@ -192,21 +192,21 @@ The following keys are defined: information about the selected set of processors. * :c:macro:`RISCV_HWPROBE_MISALIGNED_UNKNOWN`: The performance of misaligned - accesses is unknown. + scalar accesses is unknown. - * :c:macro:`RISCV_HWPROBE_MISALIGNED_EMULATED`: Misaligned accesses are + * :c:macro:`RISCV_HWPROBE_MISALIGNED_EMULATED`: Misaligned scalar accesses are emulated via software, either in or below the kernel. These accesses are always extremely slow. - * :c:macro:`RISCV_HWPROBE_MISALIGNED_SLOW`: Misaligned accesses are slower - than equivalent byte accesses. Misaligned accesses may be supported + * :c:macro:`RISCV_HWPROBE_MISALIGNED_SLOW`: Misaligned scalar accesses are + slower than equivalent byte accesses. Misaligned accesses may be supported directly in hardware, or trapped and emulated by software. - * :c:macro:`RISCV_HWPROBE_MISALIGNED_FAST`: Misaligned accesses are faster - than equivalent byte accesses. + * :c:macro:`RISCV_HWPROBE_MISALIGNED_FAST`: Misaligned scalar accesses are + faster than equivalent byte accesses. - * :c:macro:`RISCV_HWPROBE_MISALIGNED_UNSUPPORTED`: Misaligned accesses are - not supported at all and will generate a misaligned address fault. + * :c:macro:`RISCV_HWPROBE_MISALIGNED_UNSUPPORTED`: Misaligned scalar accesses + are not supported at all and will generate a misaligned address fault. * :c:macro:`RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE`: An unsigned int which represents the size of the Zicboz block in bytes. -- 2.43.0
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