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    SubjectRe: [PATCH 08/17] clk: samsung: gs101: add support for cmu_hsi2
    From
    On 04/04/2024 14:25, Peter Griffin wrote:
    > CMU_HSI2 is the clock management unit used for the hsi2 block.
    > HSI stands for High Speed Interface and as such it generates
    > clocks for PCIe, UFS and MMC card.
    >
    > This patch adds support for the muxes, dividers, and gates in
    > cmu_hsi2.
    >
    > CLK_GOUT_HSI2_HSI2_CMU_HSI2_PCLK is marked as CLK_IS_CRITICAL
    > as disabling it leads to an immediate system hang.
    >
    > CLK_GOUT_HSI2_SYSREG_HSI2_PCLK is also marked CLK_IS_CRITICAL.
    > A hang is not observed with fine grained clock control, but
    > UFS IP does not function with syscon controlling this clock
    > just around hsi2_sysreg register accesses.
    >
    > CLK_GOUT_HSI2_GPIO_HSI2_PCLK is marked CLK_IGNORE_UNUSED until
    > the exynos pinctrl clock patches land then it can be removed.
    >
    > Some clocks in this unit have very long names. To help with this
    > the clock name mangling strategy was updated to include removing
    > the following sub-strings.
    > - G4X2_DWC_PCIE_CTL_
    > - G4X1_DWC_PCIE_CTL_
    > - PCIE_SUB_CTRL_
    > - INST_0_
    > - LN05LPE_
    > - TM_WRAPPER_
    > - SF_
    >
    > Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
    >
    > ---
    > Updated regex for clock name mangling
    > sed \
    > -e 's|^PLL_LOCKTIME_PLL_\([^_]\+\)|fout_\L\1_pll|' \
    > \
    > -e 's|^PLL_CON0_MUX_CLKCMU_\([^_]\+\)_\(.*\)|mout_\L\1_\2|' \
    > -e 's|^PLL_CON0_PLL_\(.*\)|mout_pll_\L\1|' \
    > -e 's|^CLK_CON_MUX_MUX_CLK_\(.*\)|mout_\L\1|' \
    > -e '/^PLL_CON[1-4]_[^_]\+_/d' \
    > -e '/^[^_]\+_CMU_[^_]\+_CONTROLLER_OPTION/d' \
    > -e '/^CLKOUT_CON_BLK_[^_]\+_CMU_[^_]\+_CLKOUT0/d' \
    > \
    > -e 's|_IPCLKPORT||' \
    > -e 's|_RSTNSYNC||' \
    > -e 's|_G4X2_DWC_PCIE_CTL||' \
    > -e 's|_G4X1_DWC_PCIE_CTL||' \
    > -e 's|_PCIE_SUB_CTRL||' \
    > -e 's|_INST_0||g' \
    > -e 's|_LN05LPE||' \
    > -e 's|_TM_WRAPPER||' \
    > -e 's|_SF||' \
    > \
    > -e 's|^CLK_CON_DIV_DIV_CLK_\([^_]\+\)_\(.*\)|dout_\L\1_\2|' \
    > \
    > -e 's|^CLK_CON_BUF_CLKBUF_\([^_]\+\)_\(.*\)|gout_\L\1_\2|' \
    > -e 's|^CLK_CON_GAT_CLK_BLK_\([^_]\+\)_UID_\(.*\)|gout_\L\1_\2|' \
    > -e 's|^gout_[^_]\+_[^_]\+_cmu_\([^_]\+\)_pclk$|gout_\1_\1_pclk|' \
    > -e 's|^CLK_CON_GAT_GOUT_BLK_\([^_]\+\)_UID_\(.*\)|gout_\L\1_\2|' \
    > -e 's|^CLK_CON_GAT_CLK_\([^_]\+\)_\(.*\)|gout_\L\1_clk_\L\1_\2|' \
    > \
    > -e '/^\(DMYQCH\|PCH\|QCH\|QUEUE\)_/d'
    > ---
    > drivers/clk/samsung/clk-gs101.c | 558 +++++++++++++++++++++++
    > include/dt-bindings/clock/google,gs101.h | 63 +++

    Bindings are separate patches.

    > 2 files changed, 621 insertions(+)
    >
    > diff --git a/drivers/clk/samsung/clk-gs101.c b/drivers/clk/samsung/clk-gs101.c
    > index d065e343a85d..b9f84c7d5c22 100644
    > --- a/drivers/clk/samsung/clk-gs101.c
    > +++ b/drivers/clk/samsung/clk-gs101.c
    > @@ -22,6 +22,7 @@
    > #define CLKS_NR_MISC (CLK_GOUT_MISC_XIU_D_MISC_ACLK + 1)
    > #define CLKS_NR_PERIC0 (CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK + 1)
    > #define CLKS_NR_PERIC1 (CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK + 1)
    > +#define CLKS_NR_HSI2 (CLK_GOUT_HSI2_XIU_P_HSI2_ACLK + 1)
    >
    > /* ---- CMU_TOP ------------------------------------------------------------- */
    >
    > @@ -3409,6 +3410,560 @@ static const struct samsung_cmu_info peric1_cmu_info __initconst = {
    > .clk_name = "bus",
    > };
    >
    > +/* ---- CMU_HSI2 ---------------------------------------------------------- */
    > +
    > +/* Register Offset definitions for CMU_HSI2 (0x14400000) */
    > +#define PLL_CON0_MUX_CLKCMU_HSI2_BUS_USER 0x0600
    > +#define PLL_CON1_MUX_CLKCMU_HSI2_BUS_USER 0x0604
    > +#define PLL_CON0_MUX_CLKCMU_HSI2_MMC_CARD_USER 0x0610
    > +#define PLL_CON1_MUX_CLKCMU_HSI2_MMC_CARD_USER 0x0614
    > +#define PLL_CON0_MUX_CLKCMU_HSI2_PCIE_USER 0x0620
    > +#define PLL_CON1_MUX_CLKCMU_HSI2_PCIE_USER 0x0624
    > +#define PLL_CON0_MUX_CLKCMU_HSI2_UFS_EMBD_USER 0x0630
    > +#define PLL_CON1_MUX_CLKCMU_HSI2_UFS_EMBD_USER 0x0634
    > +#define HSI2_CMU_HSI2_CONTROLLER_OPTION 0x0800
    > +#define CLKOUT_CON_BLK_HSI2_CMU_HSI2_CLKOUT0 0x0810
    > +#define CLK_CON_GAT_CLK_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN 0x2000
    > +#define CLK_CON_GAT_CLK_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN 0x2004
    > +#define CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4A_1_IPCLKPORT_ACLK 0x2008
    > +#define CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4A_1_IPCLKPORT_PCLK 0x200c
    > +#define CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4B_1_IPCLKPORT_ACLK 0x2010
    > +#define CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4B_1_IPCLKPORT_PCLK 0x2014
    > +#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_D_TZPC_HSI2_IPCLKPORT_PCLK 0x201c
    > +#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_GPC_HSI2_IPCLKPORT_PCLK 0x2020
    > +#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_GPIO_HSI2_IPCLKPORT_PCLK 0x2024
    > +#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_HSI2_CMU_HSI2_IPCLKPORT_PCLK 0x2028
    > +#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_LHM_AXI_P_HSI2_IPCLKPORT_I_CLK 0x202c
    > +#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_LHS_ACEL_D_HSI2_IPCLKPORT_I_CLK 0x2030
    > +#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_MMC_CARD_IPCLKPORT_I_ACLK 0x2034
    > +#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_MMC_CARD_IPCLKPORT_SDCLKIN 0x2038
    > +#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG 0x203c
    > +#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG 0x2040
    > +#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG 0x2044
    > +#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK 0x2048
    > +#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG 0x204c
    > +#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG 0x2050
    > +#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG 0x2054
    > +#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK 0x2058
    > +#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_PHY_UDBG_I_APB_PCLK 0x205c
    > +#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_PIPE_PAL_PCIE_INST_0_I_APB_PCLK 0x2060
    > +#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_SF_PCIEPHY210X2_LN05LPE_QCH_TM_WRAPPER_INST_0_I_APB_PCLK 0x2064

    Is it doable to use shorter register names while still keeping them
    close to datasheet/manual? This one is a bit too much... actually most
    of them are quite too much. :)


    ..

    > +
    > /* ---- platform_driver ----------------------------------------------------- */
    >
    > static int __init gs101_cmu_probe(struct platform_device *pdev)
    > @@ -3432,6 +3987,9 @@ static const struct of_device_id gs101_cmu_of_match[] = {
    > }, {
    > .compatible = "google,gs101-cmu-peric1",
    > .data = &peric1_cmu_info,
    > + }, {
    > + .compatible = "google,gs101-cmu-hsi2",
    > + .data = &hsi2_cmu_info,

    Keep these also alphabetically ordered by compatible.



    Best regards,
    Krzysztof


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