| Date | Thu, 4 Apr 2024 11:26:28 +0100 | | From | Jonathan Cameron <> | | Subject | Re: [PATCH 09/26] cxl/region: Add Dynamic Capacity CXL region support |
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On Sun, 24 Mar 2024 16:18:12 -0700 ira.weiny@intel.com wrote:
> From: Navneet Singh <navneet.singh@intel.com> > > CXL devices optionally support dynamic capacity. CXL Regions must be > configured correctly to access this capacity. Similar to ram and pmem > partitions, DC Regions, as they are called in CXL 3.1, represent > different partitions of the DPA space. > > Introduce the concept of a sparse DAX region. Add the create_dc_region > sysfs entry to create sparse DC DAX regions. Special case DC capable > regions to create a 0 sized seed DAX device to maintain backwards > compatibility with older software which needs a default DAX device to > hold the region reference. > > Flag sparse DAX regions to indicate 0 capacity available until such time > as DC capacity is added. > > Interleaving is deferred in this series. Add an early check. > > Signed-off-by: Navneet Singh <navneet.singh@intel.com> > Co-developed-by: Ira Weiny <ira.weiny@intel.com> > Signed-off-by: Ira Weiny <ira.weiny@intel.com> With the -EBUSY others addressed LGTM. Fan's duplication comment might be something to tidy up later.
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
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