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SubjectRe: [PATCH 3/3] serial: sc16is7xx: add support for EXAR XR20M1172 UART
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On 18. 04. 24, 15:25, Konstantin wrote:
> From: Konstantin <ria.freelander@gmail.com>
>
> Its register set is mostly compatible with SC16IS762, but
> it has a support for additional division rates of UART
> with special DLD register. So, add handling this register
> via UPF_MAGIC_MULTIPLIER port flag.
>
> Signed-off-by: Konstantin Pugin <ria.freelander@gmail.com>
> ---
> drivers/tty/serial/sc16is7xx.c | 54 ++++++++++++++++++++++++++++++++--
> 1 file changed, 51 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/tty/serial/sc16is7xx.c b/drivers/tty/serial/sc16is7xx.c
> index a300eebf1401..7fc1c19b3891 100644
> --- a/drivers/tty/serial/sc16is7xx.c
> +++ b/drivers/tty/serial/sc16is7xx.c
> @@ -65,6 +65,7 @@
> /* Special Register set: Only if ((LCR[7] == 1) && (LCR != 0xBF)) */
> #define SC16IS7XX_DLL_REG (0x00) /* Divisor Latch Low */
> #define SC16IS7XX_DLH_REG (0x01) /* Divisor Latch High */
> +#define SC16IS7XX_DLD_REG (0x02) /* Divisor Latch Mode (only on EXAR chips) */
>
> /* Enhanced Register set: Only if (LCR == 0xBF) */
> #define SC16IS7XX_EFR_REG (0x02) /* Enhanced Features */
> @@ -218,6 +219,20 @@
> #define SC16IS7XX_TCR_RX_HALT(words) ((((words) / 4) & 0x0f) << 0)
> #define SC16IS7XX_TCR_RX_RESUME(words) ((((words) / 4) & 0x0f) << 4)
>
> +/* Divisor Latch Mode bits (EXAR extension)
> + *
> + * EXAR hardware is mostly compatible with SC16IS7XX, but supports additional feature:
> + * 4x and 8x divisor, instead of default 16x. It has a special register to program it.
> + * Bits 0 to 3 is fractional divisor, it used to set value of last 16 bits of
> + * uartclk * (16 / divisor) / baud, in case of default it will be uartclk / baud.
> + * Bits 4 and 5 used as switches, and should not be set to 1 simultaneously.
> + */
> +
> +#define SC16IS7XX_DLD_16X 0
> +#define SC16IS7XX_DLD_DIV(m) ((m) & 0xf)

Why not to use GENMASK() here and FIELD_PREP() in the code?

> +#define SC16IS7XX_DLD_8X BIT(4)
> +#define SC16IS7XX_DLD_4X BIT(5)
> +
> /*
> * TLR register bits
> * If TLR[3:0] or TLR[7:4] are logical 0, the selectable trigger levels via the
..
> @@ -559,13 +582,29 @@ static int sc16is7xx_set_baud(struct uart_port *port, int baud)
> struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
> u8 lcr;
> u8 prescaler = 0;
> - unsigned long clk = port->uartclk, div = clk / 16 / baud;
> + u8 divisor = 16;
> + u8 dld_mode = SC16IS7XX_DLD_16X;
> + bool has_dld = !!(port->flags & UPF_MAGIC_MULTIPLIER);

No need for !!.

> + unsigned long clk = port->uartclk, div, div16;

All these locals would deserve better ordering.

..
> @@ -1014,6 +1055,7 @@ static void sc16is7xx_set_termios(struct uart_port *port,
> unsigned int lcr, flow = 0;
> int baud;
> unsigned long flags;
> + bool has_dld = !!(port->flags & UPF_MAGIC_MULTIPLIER);

Ditto.

>
> kthread_cancel_delayed_work_sync(&one->ms_work);
>
thanks,
--
js
suse labs


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