Messages in this thread | | | Date | Thu, 18 Apr 2024 13:33:19 +0200 | Subject | Re: [PATCH] clk: qcom: dispcc-x1e80100: Drop the reconfiguring of PLL0 on probe | From | Konrad Dybcio <> |
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On 18.04.2024 12:51 PM, Abel Vesa wrote: > Currently, PLL0 is configured by the bootloader is the parent of the > mdp_clk_src. Reconfiguring it on probe leaves the PLL0 in "stand-by" > state (unlocked), which will trigger RCG child clocks to not update > their config,
Sounds like this is the problem that should be fixed instead.
which then breaks eDP on all x1e80100 boards. So rely > on the bootloader for now. Drop the config values as well. Also add > a comment to explain why the PLL0 is not configured alongside PLL1. > > Fixes: ee3f0739035f ("clk: qcom: Add dispcc clock driver for x1e80100") > Signed-off-by: Abel Vesa <abel.vesa@linaro.org> > ---
This works, because you have (at least) partially configured hardware, but we shouldn't assume this to be the case.
Konrad
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