Messages in this thread | | | Date | Sun, 14 Apr 2024 08:13:54 +0800 | From | Inochi Amaoto <> | Subject | Re: [PATCH] clk: sophgo: Use div64 for fpll rate calculation |
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On Sat, Apr 13, 2024 at 08:53:33AM +0800, Inochi Amaoto wrote: > The CV1800 SoC needs to use 64-bit division for fpll rate > calculation, which will cause problem on 32-bit system. > Use div64 series function to avoid this problem. > > Fixes: 80fd61ec4612 ("clk: sophgo: Add clock support for CV1800 SoC") > Signed-off-by: Inochi Amaoto <inochiama@outlook.com> > Reported-by: kernel test robot <lkp@intel.com> > Closes: https://lore.kernel.org/oe-kbuild-all/202404122344.d5pb2N1I-lkp@intel.com/
This patch can also close another report.
Closes: https://lore.kernel.org/oe-kbuild-all/202404140310.QEjZKtTN-lkp@intel.com/
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