Messages in this thread | | | Date | Thu, 11 Apr 2024 14:55:59 -0700 | Subject | Re: [RFC PATCH 34/41] KVM: x86/pmu: Intercept EVENT_SELECT MSR | From | Sean Christopherson <> |
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On Fri, Jan 26, 2024, Xiong Zhang wrote: > From: Xiong Zhang <xiong.y.zhang@intel.com> > > Event selectors for GP counters are still intercepted for the purpose of > security, i.e., preventing guest from using unallowed events to steal > information or take advantages of any CPU errata.
Heh, so then they shouldn't have been passed through in the first place.
> Signed-off-by: Xiong Zhang <xiong.y.zhang@intel.com> > Signed-off-by: Mingwei Zhang <mizhang@google.com> > --- > arch/x86/kvm/vmx/pmu_intel.c | 1 - > arch/x86/kvm/vmx/vmx.c | 1 - > 2 files changed, 2 deletions(-) > > diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c > index 9bbd5084a766..621922005184 100644 > --- a/arch/x86/kvm/vmx/pmu_intel.c > +++ b/arch/x86/kvm/vmx/pmu_intel.c > @@ -809,7 +809,6 @@ void intel_passthrough_pmu_msrs(struct kvm_vcpu *vcpu) > int i; > > for (i = 0; i < vcpu_to_pmu(vcpu)->nr_arch_gp_counters; i++) { > - vmx_set_intercept_for_msr(vcpu, MSR_ARCH_PERFMON_EVENTSEL0 + i, MSR_TYPE_RW, false); > vmx_set_intercept_for_msr(vcpu, MSR_IA32_PERFCTR0 + i, MSR_TYPE_RW, false); > if (fw_writes_is_enabled(vcpu)) > vmx_set_intercept_for_msr(vcpu, MSR_IA32_PMC0 + i, MSR_TYPE_RW, false); > diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c > index d28afa87be70..1a518800d154 100644 > --- a/arch/x86/kvm/vmx/vmx.c > +++ b/arch/x86/kvm/vmx/vmx.c > @@ -698,7 +698,6 @@ static bool is_valid_passthrough_msr(u32 msr) > case MSR_LBR_CORE_FROM ... MSR_LBR_CORE_FROM + 8: > case MSR_LBR_CORE_TO ... MSR_LBR_CORE_TO + 8: > /* LBR MSRs. These are handled in vmx_update_intercept_for_lbr_msrs() */ > - case MSR_ARCH_PERFMON_EVENTSEL0 ... MSR_ARCH_PERFMON_EVENTSEL0 + 7: > case MSR_IA32_PMC0 ... MSR_IA32_PMC0 + 7: > case MSR_IA32_PERFCTR0 ... MSR_IA32_PERFCTR0 + 7: > case MSR_CORE_PERF_FIXED_CTR_CTRL: > -- > 2.34.1 >
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