Messages in this thread | ![/](/images/icornerl.gif) | | From | "Tian, Kevin" <> | Subject | RE: [PATCH v2 1/1] iommu/vt-d: Remove caching mode check before device TLB flush | Date | Wed, 10 Apr 2024 06:14:24 +0000 |
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> From: Lu Baolu <baolu.lu@linux.intel.com> > Sent: Wednesday, April 10, 2024 1:58 PM > > The Caching Mode (CM) of the Intel IOMMU indicates if the hardware > implementation caches not-present or erroneous translation-structure > entries except the first-stage translation. The caching mode is > irrelevant to the device TLB , therefore there is no need to check > it before a device TLB invalidation operation. > > iommu_flush_iotlb_psi() is called in map and unmap paths. The caching > mode check before device TLB invalidation will cause device TLB > invalidation always issued if IOMMU is not running in caching mode. > This is wrong and causes unnecessary performance overhead. > > The removal of caching mode check in intel_flush_iotlb_all() doesn't > impact anything no matter the IOMMU is working in caching mode or not. > Commit <29b32839725f> ("iommu/vt-d: Do not use flush-queue when > caching-mode is on") has already disabled flush-queue for caching mode, > hence caching mode will never call intel_flush_iotlb_all(). > > Fixes: bf92df30df90 ("intel-iommu: Only avoid flushing device IOTLB for > domain ID 0 in caching mode") > Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
Reviewed-by: Kevin Tian <kevin.tian@intel.com>
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