Messages in this thread | ![/](/images/icornerl.gif) | | Date | Wed, 10 Apr 2024 12:55:35 -0300 | From | Jason Gunthorpe <> | Subject | Re: [PATCH v2 09/12] iommu/vt-d: Use cache helpers in arch_invalidate_secondary_tlbs |
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On Wed, Apr 10, 2024 at 10:08:41AM +0800, Lu Baolu wrote: > /* Pages have been freed at this point */ > static void intel_arch_invalidate_secondary_tlbs(struct mmu_notifier *mn, > struct mm_struct *mm, > unsigned long start, unsigned long end) > { > struct intel_svm *svm = container_of(mn, struct intel_svm, notifier); > + struct dmar_domain *domain = svm->domain; > > if (start == 0 && end == -1UL) {
ULONG_MAX ideally.
> - intel_flush_svm_all(svm); > + cache_tag_flush_all(domain); > return; > } > > - intel_flush_svm_range(svm, start, > - (end - start + PAGE_SIZE - 1) >> VTD_PAGE_SHIFT, 0); > + cache_tag_flush_range(domain, start, end, 0);
Be mindful of the note from the ARM driver:
/* * The mm_types defines vm_end as the first byte after the end address, * different from IOMMU subsystem using the last address of an address * range. So do a simple translation here by calculating size correctly. */ size = end - start;
Given that the cache_tag_flush_range's are all tied directly to the iommu gather API, this is probably missing a -1 though perhaps it does not cause a functional problem here.
Jason
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