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    SubjectRe: [PATCH v2 04/27] riscv: zicfiss/zicfilp enumeration
    On Fri, Mar 29, 2024, at 12:44 AM, Deepak Gupta wrote:
    > Adds description in dt-bindings (extensions.yaml)
    >
    > This patch adds support for detecting zicfiss and zicfilp. zicfiss and zicfilp
    > stands for unprivleged integer spec extension for shadow stack and branch
    > tracking on indirect branches, respectively.
    >
    > This patch looks for zicfiss and zicfilp in device tree and accordinlgy lights
    > up bit in cpu feature bitmap. Furthermore this patch adds detection utility
    > functions to return whether shadow stack or landing pads are supported by
    > cpu.
    >
    > Signed-off-by: Deepak Gupta <debug@rivosinc.com>
    > ---
    > .../devicetree/bindings/riscv/extensions.yaml | 10 ++++++++++
    > arch/riscv/include/asm/cpufeature.h | 13 +++++++++++++
    > arch/riscv/include/asm/hwcap.h | 2 ++
    > arch/riscv/include/asm/processor.h | 1 +
    > arch/riscv/kernel/cpufeature.c | 2 ++
    > 5 files changed, 28 insertions(+)
    >
    > diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml
    > b/Documentation/devicetree/bindings/riscv/extensions.yaml
    > index 63d81dc895e5..f8d78bf7400b 100644
    > --- a/Documentation/devicetree/bindings/riscv/extensions.yaml
    > +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
    > @@ -317,6 +317,16 @@ properties:
    > The standard Zicboz extension for cache-block zeroing as
    > ratified
    > in commit 3dd606f ("Create cmobase-v1.0.pdf") of
    > riscv-CMOs.
    >
    > + - const: zicfilp
    > + description:
    > + The standard Zicfilp extension for enforcing forward edge
    > control-flow
    > + integrity as ratified in commit 0036ff2 of riscv-cfi.
    > +
    > + - const: zicfiss
    > + description:
    > + The standard Zicfiss extension for enforcing backward edge
    > control-flow
    > + integrity as ratified in commit 0036ff2 of riscv-cfi.
    > +

    Neither of these extensions is currently ratified (the public review
    period started 15 hours ago) and the git hashes are unlikely to be
    correct for the ratified version.

    -s

    > - const: zicntr
    > description:
    > The standard Zicntr extension for base counters and
    > timers, as
    > diff --git a/arch/riscv/include/asm/cpufeature.h
    > b/arch/riscv/include/asm/cpufeature.h
    > index 0bd11862b760..f0fb8d8ae273 100644
    > --- a/arch/riscv/include/asm/cpufeature.h
    > +++ b/arch/riscv/include/asm/cpufeature.h
    > @@ -8,6 +8,7 @@
    >
    > #include <linux/bitmap.h>
    > #include <linux/jump_label.h>
    > +#include <linux/smp.h>
    > #include <asm/hwcap.h>
    > #include <asm/alternative-macros.h>
    > #include <asm/errno.h>
    > @@ -137,4 +138,16 @@ static __always_inline bool
    > riscv_cpu_has_extension_unlikely(int cpu, const unsi
    >
    > DECLARE_STATIC_KEY_FALSE(fast_misaligned_access_speed_key);
    >
    > +static inline bool cpu_supports_shadow_stack(void)
    > +{
    > + return (IS_ENABLED(CONFIG_RISCV_USER_CFI) &&
    > + riscv_cpu_has_extension_unlikely(smp_processor_id(),
    > RISCV_ISA_EXT_ZICFISS));
    > +}
    > +
    > +static inline bool cpu_supports_indirect_br_lp_instr(void)
    > +{
    > + return (IS_ENABLED(CONFIG_RISCV_USER_CFI) &&
    > + riscv_cpu_has_extension_unlikely(smp_processor_id(),
    > RISCV_ISA_EXT_ZICFILP));
    > +}
    > +
    > #endif
    > diff --git a/arch/riscv/include/asm/hwcap.h
    > b/arch/riscv/include/asm/hwcap.h
    > index 1f2d2599c655..74b6c727f545 100644
    > --- a/arch/riscv/include/asm/hwcap.h
    > +++ b/arch/riscv/include/asm/hwcap.h
    > @@ -80,6 +80,8 @@
    > #define RISCV_ISA_EXT_ZFA 71
    > #define RISCV_ISA_EXT_ZTSO 72
    > #define RISCV_ISA_EXT_ZACAS 73
    > +#define RISCV_ISA_EXT_ZICFILP 74
    > +#define RISCV_ISA_EXT_ZICFISS 75
    >
    > #define RISCV_ISA_EXT_XLINUXENVCFG 127
    >
    > diff --git a/arch/riscv/include/asm/processor.h
    > b/arch/riscv/include/asm/processor.h
    > index a8509cc31ab2..6c5b3d928b12 100644
    > --- a/arch/riscv/include/asm/processor.h
    > +++ b/arch/riscv/include/asm/processor.h
    > @@ -13,6 +13,7 @@
    > #include <vdso/processor.h>
    >
    > #include <asm/ptrace.h>
    > +#include <asm/hwcap.h>
    >
    > #ifdef CONFIG_64BIT
    > #define DEFAULT_MAP_WINDOW (UL(1) << (MMAP_VA_BITS - 1))
    > diff --git a/arch/riscv/kernel/cpufeature.c
    > b/arch/riscv/kernel/cpufeature.c
    > index 79a5a35fab96..d052cad5b82f 100644
    > --- a/arch/riscv/kernel/cpufeature.c
    > +++ b/arch/riscv/kernel/cpufeature.c
    > @@ -263,6 +263,8 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
    > __RISCV_ISA_EXT_DATA(h, RISCV_ISA_EXT_h),
    > __RISCV_ISA_EXT_SUPERSET(zicbom, RISCV_ISA_EXT_ZICBOM,
    > riscv_xlinuxenvcfg_exts),
    > __RISCV_ISA_EXT_SUPERSET(zicboz, RISCV_ISA_EXT_ZICBOZ,
    > riscv_xlinuxenvcfg_exts),
    > + __RISCV_ISA_EXT_SUPERSET(zicfilp, RISCV_ISA_EXT_ZICFILP,
    > riscv_xlinuxenvcfg_exts),
    > + __RISCV_ISA_EXT_SUPERSET(zicfiss, RISCV_ISA_EXT_ZICFISS,
    > riscv_xlinuxenvcfg_exts),
    > __RISCV_ISA_EXT_DATA(zicntr, RISCV_ISA_EXT_ZICNTR),
    > __RISCV_ISA_EXT_DATA(zicond, RISCV_ISA_EXT_ZICOND),
    > __RISCV_ISA_EXT_DATA(zicsr, RISCV_ISA_EXT_ZICSR),
    > --
    > 2.43.2
    >
    >
    > _______________________________________________
    > linux-riscv mailing list
    > linux-riscv@lists.infradead.org
    > http://lists.infradead.org/mailman/listinfo/linux-riscv

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