Messages in this thread Patch in this message | | | From | Paul Barker <> | Subject | [PATCH 2/2] clk: renesas: r9a07g044: Mark resets array as const | Date | Wed, 20 Mar 2024 08:28:31 +0000 |
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The r9a07g044_resets array describes the reset signals in this SoC and does not change at runtime.
Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com> --- drivers/clk/renesas/r9a07g044-cpg.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c index 48404cafea3f..f6df3f7a31b5 100644 --- a/drivers/clk/renesas/r9a07g044-cpg.c +++ b/drivers/clk/renesas/r9a07g044-cpg.c @@ -368,7 +368,7 @@ static const struct { #endif }; -static struct rzg2l_reset r9a07g044_resets[] = { +static const struct rzg2l_reset r9a07g044_resets[] = { DEF_RST(R9A07G044_GIC600_GICRESET_N, 0x814, 0), DEF_RST(R9A07G044_GIC600_DBG_GICRESET_N, 0x814, 1), DEF_RST(R9A07G044_IA55_RESETN, 0x818, 0), -- 2.44.0
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