Messages in this thread | ![/](/images/icornerl.gif) | | From | Dmitry Baryshkov <> | Date | Mon, 18 Mar 2024 16:16:44 +0200 | Subject | Re: [PATCH 2/5] clk: qcom: apss-ipq-pll: use an 1-D array for Huayra pll register offsets |
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On Mon, 18 Mar 2024 at 13:20, Gabor Juhos <j4g8y7@gmail.com> wrote: > > The 'ipq_pll_offsets' is defined as a two-dimensional array, but it > contains a sole element only so convert it to an one-dimensional > array. Also, rename the variable to better reflect that it is used > for the Huayra PLLs. > > No functional changes. > > Signed-off-by: Gabor Juhos <j4g8y7@gmail.com> > --- > drivers/clk/qcom/apss-ipq-pll.c | 22 ++++++++++------------ > 1 file changed, 10 insertions(+), 12 deletions(-) > > diff --git a/drivers/clk/qcom/apss-ipq-pll.c b/drivers/clk/qcom/apss-ipq-pll.c > index ed3e6405f99cb..f5c7eaf8db374 100644 > --- a/drivers/clk/qcom/apss-ipq-pll.c > +++ b/drivers/clk/qcom/apss-ipq-pll.c > @@ -13,22 +13,20 @@ > * are different from the one mentioned in the clk-alpha-pll.c, since the > * PLL is specific to APSS, so lets the define the same. > */ > -static const u8 ipq_pll_offsets[][PLL_OFF_MAX_REGS] = { > - [CLK_ALPHA_PLL_TYPE_HUAYRA] = { > - [PLL_OFF_L_VAL] = 0x08, > - [PLL_OFF_ALPHA_VAL] = 0x10, > - [PLL_OFF_USER_CTL] = 0x18, > - [PLL_OFF_CONFIG_CTL] = 0x20, > - [PLL_OFF_CONFIG_CTL_U] = 0x24, > - [PLL_OFF_STATUS] = 0x28, > - [PLL_OFF_TEST_CTL] = 0x30, > - [PLL_OFF_TEST_CTL_U] = 0x34, > - }, > +static const u8 ipq_pll_huayra_regs[PLL_OFF_MAX_REGS] = { > + [PLL_OFF_L_VAL] = 0x08, > + [PLL_OFF_ALPHA_VAL] = 0x10, > + [PLL_OFF_USER_CTL] = 0x18, > + [PLL_OFF_CONFIG_CTL] = 0x20, > + [PLL_OFF_CONFIG_CTL_U] = 0x24, > + [PLL_OFF_STATUS] = 0x28, > + [PLL_OFF_TEST_CTL] = 0x30, > + [PLL_OFF_TEST_CTL_U] = 0x34, > };
Can you please move this to clk_alpha_pll? We can then drop it from clk-cbf-8996.c too.
> > static struct clk_alpha_pll ipq_pll_huayra = { > .offset = 0x0, > - .regs = ipq_pll_offsets[CLK_ALPHA_PLL_TYPE_HUAYRA], > + .regs = ipq_pll_huayra_regs, > .flags = SUPPORTS_DYNAMIC_UPDATE, > .clkr = { > .enable_reg = 0x0, > > -- > 2.44.0 > >
-- With best wishes Dmitry
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