Messages in this thread Patch in this message | | | Date | Mon, 18 Mar 2024 10:07:37 -0000 | From | "tip-bot2 for Randy Dunlap" <> | Subject | [tip: timers/core] clocksource: arm_global_timer: fix non-kernel-doc comment |
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The following commit has been merged into the timers/core branch of tip:
Commit-ID: 97454a65d56b240013ed8d396427b85e34384238 Gitweb: https://git.kernel.org/tip/97454a65d56b240013ed8d396427b85e34384238 Author: Randy Dunlap <rdunlap@infradead.org> AuthorDate: Sun, 14 Jan 2024 21:36:41 -08:00 Committer: Daniel Lezcano <daniel.lezcano@linaro.org> CommitterDate: Wed, 21 Feb 2024 09:56:06 +01:00
clocksource: arm_global_timer: fix non-kernel-doc comment
Use a common C comment "/*" instead of a kernel-doc marker "/**" to prevent kernel-doc warnings:
arm_global_timer.c:92: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst * To ensure that updates to comparator value register do not set the arm_global_timer.c:92: warning: missing initial short description on line: * To ensure that updates to comparator value register do not set the
Signed-off-by: Randy Dunlap <rdunlap@infradead.org> Cc: Patrice Chotard <patrice.chotard@foss.st.com> Cc: linux-arm-kernel@lists.infradead.org Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Link: https://lore.kernel.org/r/20240115053641.29129-1-rdunlap@infradead.org --- drivers/clocksource/arm_global_timer.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clocksource/arm_global_timer.c b/drivers/clocksource/arm_global_timer.c index 8dd1e46..d749dee 100644 --- a/drivers/clocksource/arm_global_timer.c +++ b/drivers/clocksource/arm_global_timer.c @@ -88,7 +88,7 @@ static u64 gt_counter_read(void) return _gt_counter_read(); } -/** +/* * To ensure that updates to comparator value register do not set the * Interrupt Status Register proceed as follows: * 1. Clear the Comp Enable bit in the Timer Control Register.
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