Messages in this thread |  | | Date | Fri, 15 Mar 2024 13:08:58 +0800 | | Subject | Re: [RFC PATCH 4/6] PCI/AER: Extend RCH RAS error handling to support VH topology case | | From | "Li, Ming" <> |
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On 3/15/2024 12:05 PM, Dan Williams wrote: > Li, Ming wrote: >> On 3/15/2024 10:30 AM, Dan Williams wrote: >>> Li Ming wrote: >>>> When RCEC captures CXL.cachemem protocol errors detected by CXL root >>>> port, the recommendation from CXL r3.1 9.18.1.5 is : >>>> >>>> "Probe all CXL Downstream Ports and determine whether they have logged an >>>> error in the CXL.io or CXL.cachemem status registers." >>>> >>>> The flow is similar with RCH RAS error handling, so reuse it to support >>>> above case. >>>> >>>> Signed-off-by: Li Ming <ming4.li@intel.com> >>>> --- >>>> drivers/pci/pcie/aer.c | 20 ++++++++++++-------- >>>> 1 file changed, 12 insertions(+), 8 deletions(-) >>>> >>>> diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c >>>> index 364c74e47273..79bfa5fb78f4 100644 >>>> --- a/drivers/pci/pcie/aer.c >>>> +++ b/drivers/pci/pcie/aer.c >>>> @@ -996,11 +996,15 @@ static bool is_internal_error(struct aer_err_info *info) >>>> return info->status & PCI_ERR_UNC_INTN; >>>> } >>>> >>>> -static int cxl_rch_handle_error_iter(struct pci_dev *dev, void *data) >>>> +static int cxl_handle_error_iter(struct pci_dev *dev, void *data) >>>> { >>>> struct aer_err_info *info = (struct aer_err_info *)data; >>>> const struct pci_error_handlers *err_handler; >>>> >>>> + /* Skip the RCiEP devices not associating with RCEC */ >>>> + if ((pci_pcie_type(dev) == PCI_EXP_TYPE_RC_END) && >>>> + !dev->rcec) >>>> + return 0; >>>> if (!is_cxl_mem_dev(dev) || !cxl_error_is_native(dev)) >>>> return 0; >>> >>> is_cxl_mem_dev(dev) will always be false in the VH case, so how does >>> this change help the VH case? >> >> Hi Dan, >> >> I think it won't be false if the CXL memory device is an endpoint. >> pcie_walk_rcec_all() will walk all pci_dev in RCEC assocaited bus ranges. So these two checkings can help us to filter: >> 1. CXL memory device is an RCiEP associated with RCEC in the RCH case >> 2. CXL memory device is not an RCiEP, so it should be an endpoint in the VH case. > > It will be an endpoint, but I though cxl_handle_error_iter() is only > called for RCIEPs and RPs that are share a bus range with the RCEC. The > endpoint in the VH case is downstream of the RP. > > I had been assuming that pci_walk_bus() limits itself to buses within > the Root Complex however it descends the entire bus hierarchy so this > implementation will walk the entire topology on all root ports > associated with the RCEC looking for any CXL device. That feels wrong. > > I would expect that this limits it self to only finding root ports and > then only proceeding if that root port has a directly attached CXL > device. > Got it, will change it in v2, thank you.
> Note, when you send a v2 of this RFC be sure to copy linux-pci for these > core changes to PCI error handling. Sure, I made a mistake here.
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