Messages in this thread | | | Date | Wed, 13 Mar 2024 19:15:22 +0800 | Subject | Re: [PATCH 3/4] arm64: dts: add support for A4 based Amlogic BA400 | From | Xianwei Zhao <> |
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Hi Krzysztof, Thanks for your reivew.
On 2024/3/12 19:07, Krzysztof Kozlowski wrote: > [ EXTERNAL EMAIL ] > > On 12/03/2024 10:18, Xianwei Zhao via B4 Relay wrote: >> From: Xianwei Zhao <xianwei.zhao@amlogic.com> >> >> Amlogic A4 is an application processor designed for smart audio >> and IoT applications. >> >> Add basic support for the A4 based Amlogic BA400 board, which describes >> the following components: CPU, GIC, IRQ, Timer and UART. >> These are capable of booting up into the serial console. >> >> Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com> >> --- >> arch/arm64/boot/dts/amlogic/Makefile | 1 + >> .../boot/dts/amlogic/amlogic-a4-a113l2-ba400.dts | 43 ++++++++++ >> arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi | 99 ++++++++++++++++++++++ >> 3 files changed, 143 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/amlogic/Makefile >> index 1ab160bf928a..9a50ec11bb8d 100644 >> --- a/arch/arm64/boot/dts/amlogic/Makefile >> +++ b/arch/arm64/boot/dts/amlogic/Makefile >> @@ -1,4 +1,5 @@ >> # SPDX-License-Identifier: GPL-2.0 >> +dtb-$(CONFIG_ARCH_MESON) += amlogic-a4-a113l2-ba400.dtb >> dtb-$(CONFIG_ARCH_MESON) += amlogic-c3-c302x-aw409.dtb >> dtb-$(CONFIG_ARCH_MESON) += amlogic-t7-a311d2-an400.dtb >> dtb-$(CONFIG_ARCH_MESON) += amlogic-t7-a311d2-khadas-vim4.dtb >> diff --git a/arch/arm64/boot/dts/amlogic/amlogic-a4-a113l2-ba400.dts b/arch/arm64/boot/dts/amlogic/amlogic-a4-a113l2-ba400.dts >> new file mode 100644 >> index 000000000000..60f9f23858c6 >> --- /dev/null >> +++ b/arch/arm64/boot/dts/amlogic/amlogic-a4-a113l2-ba400.dts >> @@ -0,0 +1,43 @@ >> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) >> +/* >> + * Copyright (c) 2024 Amlogic, Inc. All rights reserved. >> + */ >> + >> +/dts-v1/; >> + >> +#include "amlogic-a4.dtsi" >> + >> +/ { >> + model = "Amlogic A113L2 ba400 Development Board"; >> + compatible = "amlogic,ba400","amlogic,a4"; >> + interrupt-parent = <&gic>; >> + #address-cells = <2>; >> + #size-cells = <2>; >> + >> + aliases { >> + serial0 = &uart_b; >> + }; >> + >> + memory@0 { >> + device_type = "memory"; >> + reg = <0x0 0x0 0x0 0x40000000>; >> + }; >> + >> + reserved-memory { >> + #address-cells = <2>; >> + #size-cells = <2>; >> + ranges; >> + >> + /* 52 MiB reserved for ARM Trusted Firmware */ >> + secmon_reserved:linux,secmon { > > Missing space after:, unusual format of node name. Are you sure this > fits DTS coding convention? > Will fix it. >> + compatible = "shared-dma-pool"; >> + no-map; >> + alignment = <0x0 0x400000>; >> + reg = <0x0 0x05000000 0x0 0x3400000>; >> + }; >> + }; >> +}; >> + >> +&uart_b { >> + status = "okay"; >> +}; >> diff --git a/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi >> new file mode 100644 >> index 000000000000..7e8745010b52 >> --- /dev/null >> +++ b/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi >> @@ -0,0 +1,99 @@ >> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) >> +/* >> + * Copyright (c) 2024 Amlogic, Inc. All rights reserved. >> + */ >> + >> +#include <dt-bindings/interrupt-controller/irq.h> >> +#include <dt-bindings/interrupt-controller/arm-gic.h> >> +#include <dt-bindings/gpio/gpio.h> >> +/ { >> + cpus { >> + #address-cells = <2>; >> + #size-cells = <0>; >> + >> + cpu0: cpu@0 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a53"; >> + reg = <0x0 0x0>; >> + enable-method = "psci"; >> + }; >> + >> + cpu1: cpu@1 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a53"; >> + reg = <0x0 0x1>; >> + enable-method = "psci"; >> + }; >> + >> + cpu2: cpu@2 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a53"; >> + reg = <0x0 0x2>; >> + enable-method = "psci"; >> + }; >> + >> + cpu3: cpu@3 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a53"; >> + reg = <0x0 0x3>; >> + enable-method = "psci"; >> + }; >> + }; >> + >> + timer { >> + compatible = "arm,armv8-timer"; >> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, >> + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, >> + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, >> + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; >> + }; >> + >> + psci { >> + compatible = "arm,psci-0.2"; >> + method = "smc"; >> + }; >> + >> + xtal: xtal-clk { >> + compatible = "fixed-clock"; >> + clock-frequency = <24000000>; >> + clock-output-names = "xtal"; >> + #clock-cells = <0>; >> + }; >> + >> + soc { >> + compatible = "simple-bus"; >> + #address-cells = <2>; >> + #size-cells = <2>; >> + ranges; >> + >> + gic: interrupt-controller@fff01000 { >> + compatible = "arm,gic-400"; >> + #interrupt-cells = <3>; >> + #address-cells = <0>; >> + interrupt-controller; >> + reg = <0x0 0xfff01000 0 0x1000>, >> + <0x0 0xfff02000 0 0x2000>, >> + <0x0 0xfff04000 0 0x2000>, >> + <0x0 0xfff06000 0 0x2000>; > > Odd order of properties... reg is usually the second. Yes. Will fix it. > > > > Best regards, > Krzysztof >
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