Messages in this thread Patch in this message | | | Date | Wed, 13 Mar 2024 22:59:13 -0700 | Subject | [PATCH v3 14/20] perf jevents: Add Miss Level Parallelism (MLP) metric for Intel | From | Ian Rogers <> |
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Number of outstanding load misses per cycle.
Signed-off-by: Ian Rogers <irogers@google.com> --- tools/perf/pmu-events/intel_metrics.py | 15 +++++++++++++++ 1 file changed, 15 insertions(+)
diff --git a/tools/perf/pmu-events/intel_metrics.py b/tools/perf/pmu-events/intel_metrics.py index da97a1781be7..6a864c0b863a 100755 --- a/tools/perf/pmu-events/intel_metrics.py +++ b/tools/perf/pmu-events/intel_metrics.py @@ -595,6 +595,20 @@ def IntelL2() -> Optional[MetricGroup]: ], description = "L2 data cache analysis") +def IntelMlp() -> Optional[Metric]: + try: + l1d = Event("L1D_PEND_MISS.PENDING") + l1dc = Event("L1D_PEND_MISS.PENDING_CYCLES") + except: + return None + + l1dc = Select(l1dc / 2, Literal("#smt_on"), l1dc) + ml = d_ratio(l1d, l1dc) + return Metric("mlp", + "Miss level parallelism - number of outstanding load misses per cycle (higher is better)", + ml, "load_miss_pending/cycle") + + def IntelPorts() -> Optional[MetricGroup]: pipeline_events = json.load(open(f"{_args.events_path}/x86/{_args.model}/pipeline.json")) @@ -796,6 +810,7 @@ def main() -> None: IntelIlp(), IntelL2(), IntelLdSt(), + IntelMlp(), IntelPorts(), IntelSwpf(), ]) -- 2.44.0.278.ge034bb2e1d-goog
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