Messages in this thread | | | From | Atish Kumar Patra <> | Date | Tue, 12 Mar 2024 12:08:38 -0700 | Subject | Re: [PATCH v3] clocksource: timer-riscv: Clear timer interrupt on timer initialization |
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On Tue, Mar 12, 2024 at 10:40 AM Samuel Holland <samuel.holland@sifive.com> wrote: > > On 2024-03-06 11:23 AM, Ley Foon Tan wrote: > > In the RISC-V specification, the stimecmp register doesn't have a default > > value. To prevent the timer interrupt from being triggered during timer > > initialization, clear the timer interrupt by writing stimecmp with a > > maximum value. > > > > Fixes: 9f7a8ff6391f ("RISC-V: Prefer sstc extension if available") > > Cc: <stable@vger.kernel.org> > > Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com> > > > > --- > > v3: > > Resolved comment from Samuel Holland. > > - Function riscv_clock_event_stop() needs to be called before > > clockevents_config_and_register(), move riscv_clock_event_stop(). > > > > v2: > > Resolved comments from Anup. > > - Moved riscv_clock_event_stop() to riscv_timer_starting_cpu(). > > - Added Fixes tag > > --- > > drivers/clocksource/timer-riscv.c | 3 +++ > > 1 file changed, 3 insertions(+) > > Reviewed-by: Samuel Holland <samuel.holland@sifive.com> > Tested-by: Samuel Holland <samuel.holland@sifive.com> >
Reviewed-by: Atish Patra <atishp@rivosinc.com>
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