Messages in this thread | ![/](/images/icornerl.gif) | | From | Ard Biesheuvel <> | Date | Fri, 1 Mar 2024 11:01:33 +0100 | Subject | Re: [PATCH v7 2/9] x86/startup_64: Defer assignment of 5-level paging global variables |
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On Wed, 28 Feb 2024 at 21:56, Borislav Petkov <bp@alien8.de> wrote: > > On Tue, Feb 27, 2024 at 04:19:10PM +0100, Ard Biesheuvel wrote: > > From: Ard Biesheuvel <ardb@kernel.org> > > > > Assigning the 5-level paging related global variables from the earliest > > C code using explicit references that use the 1:1 translation of memory > > is unnecessary, as the startup code itself does not rely on them to > > create the initial page tables, and this is all it should be doing. So > > defer these assignments to the primary C entry code that executes via > > the ordinary kernel virtual mapping. > > > > Signed-off-by: Ard Biesheuvel <ardb@kernel.org> > > --- > > arch/x86/include/asm/pgtable_64_types.h | 2 +- > > arch/x86/kernel/head64.c | 44 +++++++------------- > > 2 files changed, 15 insertions(+), 31 deletions(-) > > Reviewed-by: Borislav Petkov (AMD) <bp@alien8.de> > > Those should probably be tested on a 5level machine, just in case. >
I have tested this myself on QEMU with -cpu qemu64,+la57 and -cpu host+kvm using - EFI boot (OVMF) - legacy BIOS boot (SeaBIOS) - with and without no5lvl on the command line - with and without CONFIG_X86_5LEVEL
The scenario that I have not managed to test is entering from EFI with 5 levels of paging enabled, and switching back to 4 levels (which should work regardless of CONFIG_X86_5LEVEL). However, no firmware in existence actually supports that today, and I am pretty sure that this code has never been tested under those conditions to begin with. (OVMF patches are under review atm to allow 5-level paging to be enabled in the firmware)
I currently don't have access to real hardware with LA57 support so any additional coverage there is highly appreciated (same for the last patch in this series)
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