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Subject[PATCH 1/5] dt-bindings: clock: qcom: Add video clock bindings for SM8650
Date
Extend device tree bindings of SM8450 videocc to add support for SM8650
videocc. While it at, fix the incorrect header include in sm8450 videocc
yaml documentation.

Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
---
.../devicetree/bindings/clock/qcom,sm8450-videocc.yaml | 4 +++-
include/dt-bindings/clock/qcom,sm8450-videocc.h | 8 +++++++-
2 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml
index bad8f019a8d3..79f55620eb70 100644
--- a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml
@@ -8,18 +8,20 @@ title: Qualcomm Video Clock & Reset Controller on SM8450

maintainers:
- Taniya Das <quic_tdas@quicinc.com>
+ - Jagadeesh Kona <quic_jkona@quicinc.com>

description: |
Qualcomm video clock control module provides the clocks, resets and power
domains on SM8450.

- See also:: include/dt-bindings/clock/qcom,videocc-sm8450.h
+ See also:: include/dt-bindings/clock/qcom,sm8450-videocc.h

properties:
compatible:
enum:
- qcom,sm8450-videocc
- qcom,sm8550-videocc
+ - qcom,sm8650-videocc

reg:
maxItems: 1
diff --git a/include/dt-bindings/clock/qcom,sm8450-videocc.h b/include/dt-bindings/clock/qcom,sm8450-videocc.h
index 9d795adfe4eb..ecfebe52e4bb 100644
--- a/include/dt-bindings/clock/qcom,sm8450-videocc.h
+++ b/include/dt-bindings/clock/qcom,sm8450-videocc.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
- * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
*/

#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8450_H
@@ -19,6 +19,11 @@
#define VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC 9
#define VIDEO_CC_PLL0 10
#define VIDEO_CC_PLL1 11
+#define VIDEO_CC_MVS0_SHIFT_CLK 12
+#define VIDEO_CC_MVS0C_SHIFT_CLK 13
+#define VIDEO_CC_MVS1_SHIFT_CLK 14
+#define VIDEO_CC_MVS1C_SHIFT_CLK 15
+#define VIDEO_CC_XO_CLK_SRC 16

/* VIDEO_CC power domains */
#define VIDEO_CC_MVS0C_GDSC 0
@@ -34,5 +39,6 @@
#define CVP_VIDEO_CC_MVS1C_BCR 4
#define VIDEO_CC_MVS0C_CLK_ARES 5
#define VIDEO_CC_MVS1C_CLK_ARES 6
+#define VIDEO_CC_XO_CLK_ARES 7

#endif
--
2.43.0

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