Messages in this thread | | | Date | Thu, 29 Feb 2024 21:55:04 +0800 | Subject | Re: [PATCH 04/21] KVM: x86/mmu: Allow non-zero value for non-present SPTE and removed SPTE | From | Xiaoyao Li <> |
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On 2/28/2024 7:20 AM, Paolo Bonzini wrote: > From: Sean Christopherson <seanjc@google.com> > > For TD guest, the current way to emulate MMIO doesn't work any more, as KVM > is not able to access the private memory of TD guest and do the emulation. > Instead, TD guest expects to receive #VE when it accesses the MMIO and then > it can explicitly make hypercall to KVM to get the expected information. > > To achieve this, the TDX module always enables "EPT-violation #VE" in the > VMCS control. And accordingly, for the MMIO spte for the shared GPA, > 1. KVM needs to set "suppress #VE" bit for the non-present SPTE so that EPT > violation happens on TD accessing MMIO range. 2. On EPT violation, KVM > sets the MMIO spte to clear "suppress #VE" bit so the TD guest can receive > the #VE instead of EPT misconfiguration unlike VMX case. For the shared GPA > that is not populated yet, EPT violation need to be triggered when TD guest > accesses such shared GPA. The non-present SPTE value for shared GPA should > set "suppress #VE" bit. > > Add "suppress #VE" bit (bit 63) to SHADOW_NONPRESENT_VALUE and > REMOVED_SPTE. Unconditionally set the "suppress #VE" bit (which is bit 63) > for both AMD and Intel as: 1) AMD hardware doesn't use this bit when > present bit is off; 2) for normal VMX guest, KVM never enables the > "EPT-violation #VE" in VMCS control and "suppress #VE" bit is ignored by > hardware. > > Signed-off-by: Sean Christopherson <seanjc@google.com> > Signed-off-by: Isaku Yamahata <isaku.yamahata@intel.com> > Reviewed-by: Binbin Wu <binbin.wu@linux.intel.com> > Message-Id: <a99cb866897c7083430dce7f24c63b17d7121134.1705965635.git.isaku.yamahata@intel.com> > Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
+ 1 to the nit pointed by Yilun,
after that,
Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com>
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