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    Subject[PATCH v19 114/130] KVM: TDX: Handle MSR IA32_FEAT_CTL MSR and IA32_MCG_EXT_CTL
    Date
    From: Isaku Yamahata <isaku.yamahata@intel.com>

    MCE and MCA is advertised via cpuid based on the TDX module spec. Guest
    kernel can access IA32_FEAT_CTL for checking if LMCE is enabled by platform
    and IA32_MCG_EXT_CTL to enable LMCE. Make TDX KVM handle them. Otherwise
    guest MSR access to them with TDG.VP.VMCALL<MSR> on VE results in GP in
    guest.

    Because LMCE is disabled with qemu by default, "-cpu lmce=on" to qemu
    command line is needed to reproduce it.

    Signed-off-by: Isaku Yamahata <isaku.yamahata@intel.com>
    ---
    arch/x86/kvm/vmx/tdx.c | 20 ++++++++++++++++++++
    1 file changed, 20 insertions(+)

    diff --git a/arch/x86/kvm/vmx/tdx.c b/arch/x86/kvm/vmx/tdx.c
    index 2bddaef495d1..3481c0b6ef2c 100644
    --- a/arch/x86/kvm/vmx/tdx.c
    +++ b/arch/x86/kvm/vmx/tdx.c
    @@ -1952,6 +1952,7 @@ bool tdx_has_emulated_msr(u32 index, bool write)
    default:
    return true;
    }
    + case MSR_IA32_FEAT_CTL:
    case MSR_IA32_APICBASE:
    case MSR_EFER:
    return !write;
    @@ -1966,6 +1967,20 @@ bool tdx_has_emulated_msr(u32 index, bool write)
    int tdx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
    {
    switch (msr->index) {
    + case MSR_IA32_FEAT_CTL:
    + /*
    + * MCE and MCA are advertised via cpuid. guest kernel could
    + * check if LMCE is enabled or not.
    + */
    + msr->data = FEAT_CTL_LOCKED;
    + if (vcpu->arch.mcg_cap & MCG_LMCE_P)
    + msr->data |= FEAT_CTL_LMCE_ENABLED;
    + return 0;
    + case MSR_IA32_MCG_EXT_CTL:
    + if (!msr->host_initiated && !(vcpu->arch.mcg_cap & MCG_LMCE_P))
    + return 1;
    + msr->data = vcpu->arch.mcg_ext_ctl;
    + return 0;
    case MSR_MTRRcap:
    /*
    * Override kvm_mtrr_get_msr() which hardcodes the value.
    @@ -1984,6 +1999,11 @@ int tdx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
    int tdx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
    {
    switch (msr->index) {
    + case MSR_IA32_MCG_EXT_CTL:
    + if (!msr->host_initiated && !(vcpu->arch.mcg_cap & MCG_LMCE_P))
    + return 1;
    + vcpu->arch.mcg_ext_ctl = msr->data;
    + return 0;
    case MSR_MTRRdefType:
    /*
    * Allow writeback only for all memory.
    --
    2.25.1

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