Messages in this thread | | | Date | Mon, 15 Jan 2024 16:39:55 +0100 | From | Andrea Parri <> | Subject | Re: [PATCH v2 0/2] riscv: enable lockless lockref implementation |
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On Sat, Dec 02, 2023 at 10:03:21PM +0800, Jisheng Zhang wrote: > This series selects ARCH_USE_CMPXCHG_LOCKREF to enable the > cmpxchg-based lockless lockref implementation for riscv. Then, > implement arch_cmpxchg64_{relaxed|acquire|release}. > > After patch1: > Using Linus' test case[1] on TH1520 platform, I see a 11.2% improvement. > On JH7110 platform, I see 12.0% improvement. > > After patch2: > on both TH1520 and JH7110 platforms, I didn't see obvious > performance improvement with Linus' test case [1]. IMHO, this may > be related with the fence and lr.d/sc.d hw implementations. In theory, > lr/sc without fence could give performance improvement over lr/sc plus > fence, so add the code here to leave performance improvement room on > newer HW platforms. > > Link: http://marc.info/?l=linux-fsdevel&m=137782380714721&w=4 [1] > > Since v1: > - only select ARCH_USE_CMPXCHG_LOCKREF if 64BIT > > Jisheng Zhang (2): > riscv: select ARCH_USE_CMPXCHG_LOCKREF > riscv: cmpxchg: implement arch_cmpxchg64_{relaxed|acquire|release}
For the series,
Reviewed-by: Andrea Parri <parri.andrea@gmail.com> # code audit, QEMU tests
Andrea
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