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    Subject[PATCH v5 1/9] iommu/arm-smmu-v3: Move ctx_desc out of s1_cfg
    From
    s1_cfg describes the CD table that is inserted into an SMMU's STEs. It's
    weird for s1_cfg to also own ctx_desc which describes a CD that is
    inserted into that table. It is more appropriate for arm_smmu_domain to
    own ctx_desc.

    Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
    Reviewed-by: Nicolin Chen <nicolinc@nvidia.com>
    Signed-off-by: Michael Shavit <mshavit@google.com>
    ---

    (no changes since v2)

    Changes in v2:
    - Undo over-reaching column alignment change

    .../iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c | 2 +-
    drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 23 ++++++++++---------
    drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 6 +++--
    3 files changed, 17 insertions(+), 14 deletions(-)

    diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c
    index a5a63b1c947eb..968559d625c40 100644
    --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c
    +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c
    @@ -62,7 +62,7 @@ arm_smmu_share_asid(struct mm_struct *mm, u16 asid)
    return cd;
    }

    - smmu_domain = container_of(cd, struct arm_smmu_domain, s1_cfg.cd);
    + smmu_domain = container_of(cd, struct arm_smmu_domain, cd);
    smmu = smmu_domain->smmu;

    ret = xa_alloc(&arm_smmu_asid_xa, &new_asid, cd,
    diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
    index 9b0dc35056019..bb277ff86f65f 100644
    --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
    +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
    @@ -1869,7 +1869,7 @@ static void arm_smmu_tlb_inv_context(void *cookie)
    * careful, 007.
    */
    if (smmu_domain->stage == ARM_SMMU_DOMAIN_S1) {
    - arm_smmu_tlb_inv_asid(smmu, smmu_domain->s1_cfg.cd.asid);
    + arm_smmu_tlb_inv_asid(smmu, smmu_domain->cd.asid);
    } else {
    cmd.opcode = CMDQ_OP_TLBI_S12_VMALL;
    cmd.tlbi.vmid = smmu_domain->s2_cfg.vmid;
    @@ -1957,7 +1957,7 @@ static void arm_smmu_tlb_inv_range_domain(unsigned long iova, size_t size,
    if (smmu_domain->stage == ARM_SMMU_DOMAIN_S1) {
    cmd.opcode = smmu_domain->smmu->features & ARM_SMMU_FEAT_E2H ?
    CMDQ_OP_TLBI_EL2_VA : CMDQ_OP_TLBI_NH_VA;
    - cmd.tlbi.asid = smmu_domain->s1_cfg.cd.asid;
    + cmd.tlbi.asid = smmu_domain->cd.asid;
    } else {
    cmd.opcode = CMDQ_OP_TLBI_S2_IPA;
    cmd.tlbi.vmid = smmu_domain->s2_cfg.vmid;
    @@ -2088,7 +2088,7 @@ static void arm_smmu_domain_free(struct iommu_domain *domain)
    mutex_lock(&arm_smmu_asid_lock);
    if (cfg->cdcfg.cdtab)
    arm_smmu_free_cd_tables(smmu_domain);
    - arm_smmu_free_asid(&cfg->cd);
    + arm_smmu_free_asid(&smmu_domain->cd);
    mutex_unlock(&arm_smmu_asid_lock);
    } else {
    struct arm_smmu_s2_cfg *cfg = &smmu_domain->s2_cfg;
    @@ -2107,13 +2107,14 @@ static int arm_smmu_domain_finalise_s1(struct arm_smmu_domain *smmu_domain,
    u32 asid;
    struct arm_smmu_device *smmu = smmu_domain->smmu;
    struct arm_smmu_s1_cfg *cfg = &smmu_domain->s1_cfg;
    + struct arm_smmu_ctx_desc *cd = &smmu_domain->cd;
    typeof(&pgtbl_cfg->arm_lpae_s1_cfg.tcr) tcr = &pgtbl_cfg->arm_lpae_s1_cfg.tcr;

    - refcount_set(&cfg->cd.refs, 1);
    + refcount_set(&cd->refs, 1);

    /* Prevent SVA from modifying the ASID until it is written to the CD */
    mutex_lock(&arm_smmu_asid_lock);
    - ret = xa_alloc(&arm_smmu_asid_xa, &asid, &cfg->cd,
    + ret = xa_alloc(&arm_smmu_asid_xa, &asid, cd,
    XA_LIMIT(1, (1 << smmu->asid_bits) - 1), GFP_KERNEL);
    if (ret)
    goto out_unlock;
    @@ -2126,23 +2127,23 @@ static int arm_smmu_domain_finalise_s1(struct arm_smmu_domain *smmu_domain,
    if (ret)
    goto out_free_asid;

    - cfg->cd.asid = (u16)asid;
    - cfg->cd.ttbr = pgtbl_cfg->arm_lpae_s1_cfg.ttbr;
    - cfg->cd.tcr = FIELD_PREP(CTXDESC_CD_0_TCR_T0SZ, tcr->tsz) |
    + cd->asid = (u16)asid;
    + cd->ttbr = pgtbl_cfg->arm_lpae_s1_cfg.ttbr;
    + cd->tcr = FIELD_PREP(CTXDESC_CD_0_TCR_T0SZ, tcr->tsz) |
    FIELD_PREP(CTXDESC_CD_0_TCR_TG0, tcr->tg) |
    FIELD_PREP(CTXDESC_CD_0_TCR_IRGN0, tcr->irgn) |
    FIELD_PREP(CTXDESC_CD_0_TCR_ORGN0, tcr->orgn) |
    FIELD_PREP(CTXDESC_CD_0_TCR_SH0, tcr->sh) |
    FIELD_PREP(CTXDESC_CD_0_TCR_IPS, tcr->ips) |
    CTXDESC_CD_0_TCR_EPD1 | CTXDESC_CD_0_AA64;
    - cfg->cd.mair = pgtbl_cfg->arm_lpae_s1_cfg.mair;
    + cd->mair = pgtbl_cfg->arm_lpae_s1_cfg.mair;

    /*
    * Note that this will end up calling arm_smmu_sync_cd() before
    * the master has been added to the devices list for this domain.
    * This isn't an issue because the STE hasn't been installed yet.
    */
    - ret = arm_smmu_write_ctx_desc(smmu_domain, 0, &cfg->cd);
    + ret = arm_smmu_write_ctx_desc(smmu_domain, 0, cd);
    if (ret)
    goto out_free_cd_tables;

    @@ -2152,7 +2153,7 @@ static int arm_smmu_domain_finalise_s1(struct arm_smmu_domain *smmu_domain,
    out_free_cd_tables:
    arm_smmu_free_cd_tables(smmu_domain);
    out_free_asid:
    - arm_smmu_free_asid(&cfg->cd);
    + arm_smmu_free_asid(cd);
    out_unlock:
    mutex_unlock(&arm_smmu_asid_lock);
    return ret;
    diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
    index dcab85698a4e2..f841383a55a35 100644
    --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
    +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
    @@ -599,7 +599,6 @@ struct arm_smmu_ctx_desc_cfg {

    struct arm_smmu_s1_cfg {
    struct arm_smmu_ctx_desc_cfg cdcfg;
    - struct arm_smmu_ctx_desc cd;
    u8 s1fmt;
    u8 s1cdmax;
    };
    @@ -724,7 +723,10 @@ struct arm_smmu_domain {

    enum arm_smmu_domain_stage stage;
    union {
    - struct arm_smmu_s1_cfg s1_cfg;
    + struct {
    + struct arm_smmu_ctx_desc cd;
    + struct arm_smmu_s1_cfg s1_cfg;
    + };
    struct arm_smmu_s2_cfg s2_cfg;
    };

    --
    2.41.0.640.ga95def55d0-goog
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