Messages in this thread Patch in this message | | | From | Jia Jie Ho <> | Subject | [PATCH v2 2/2] riscv: dts: starfive - Add hwrng node for JH7110 SoC | Date | Tue, 8 Aug 2023 22:15:58 +0800 |
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Add hardware rng controller node for StarFive JH7110 SoC.
Co-developed-by: Jenny Zhang <jenny.zhang@starfivetech.com> Signed-off-by: Jenny Zhang <jenny.zhang@starfivetech.com> Signed-off-by: Jia Jie Ho <jiajie.ho@starfivetech.com> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> --- arch/riscv/boot/dts/starfive/jh7110.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+)
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi index 76046ca533ce..70d107bdcc10 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -848,6 +848,16 @@ sdma: dma-controller@16008000 { #dma-cells = <2>; }; + rng: rng@1600c000 { + compatible = "starfive,jh7110-trng"; + reg = <0x0 0x1600C000 0x0 0x4000>; + clocks = <&stgcrg JH7110_STGCLK_SEC_AHB>, + <&stgcrg JH7110_STGCLK_SEC_MISC_AHB>; + clock-names = "hclk", "ahb"; + resets = <&stgcrg JH7110_STGRST_SEC_AHB>; + interrupts = <30>; + }; + gmac0: ethernet@16030000 { compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20"; reg = <0x0 0x16030000 0x0 0x10000>; -- 2.34.1
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