Messages in this thread | ![/](/images/icornerl.gif) | | Date | Tue, 1 Aug 2023 09:42:48 +0300 | Subject | Re: [PATCH] mips: dts: ralink: reorder MT7621 clocks in Ethernet block | From | Arınç ÜNAL <> |
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I haven't received anything arguing with this so my answer is still no.
Also, this patch changes the lines introduced with b2f471a26721 ("staging: mt7621-dts: make use of new 'mt7621-clk'").
Arınç
On 29.07.2023 17:08, Arınç ÜNAL wrote: > On 29.07.2023 14:04, Rafał Miłecki wrote: >> From: Rafał Miłecki <rafal@milecki.pl> >> >> Use order as specified in the binding (first "ethif" then "fe"). >> >> This fixes: >> arch/mips/boot/dts/ralink/mt7621-tplink-hc220-g5-v1.dtb: >> ethernet@1e100000: clock-names:0: 'ethif' was expected >> From schema: >> Documentation/devicetree/bindings/net/mediatek,net.yaml >> arch/mips/boot/dts/ralink/mt7621-tplink-hc220-g5-v1.dtb: >> ethernet@1e100000: clock-names:1: 'fe' was expected >> From schema: >> Documentation/devicetree/bindings/net/mediatek,net.yaml >> >> Fixes: 7a6ee0bbab25 ("mips: dts: ralink: add MT7621 SoC") >> Signed-off-by: Rafał Miłecki <rafal@milecki.pl> > > I'm not sure if I should agree with this patch. The relevant parts of > the schema for mediatek,mt7621-eth were added way later than the > existing bindings on mt7621.dtsi. Why don't we address this on the > schema along with a bunch of other issues the patch for > mediatek,mt7621-eth brought? > > Arınç
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