Messages in this thread | ![/](/images/icornerl.gif) | | Date | Tue, 4 Jul 2023 11:39:29 +0200 | Subject | Re: [RESEND v1 2/2] riscv: dts: starfive: Add spi node for JH7110 SoC | From | Krzysztof Kozlowski <> |
| |
On 04/07/2023 11:22, William Qiu wrote: > Add spi node for JH7110 SoC. > > Co-developed-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Missing SoB.
> Signed-off-by: William Qiu <william.qiu@starfivetech.com> > --- > .../jh7110-starfive-visionfive-2.dtsi | 52 ++++++++++ > arch/riscv/boot/dts/starfive/jh7110.dtsi | 98 +++++++++++++++++++ > 2 files changed, 150 insertions(+) > > diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi > index 2a6d81609284..a066d2e399c4 100644 > --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi > +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi > @@ -126,6 +126,20 @@ &i2c6 { > status = "okay"; > }; > > +&spi0 { > + pinctrl-names = "default"; > + pinctrl-0 = <&spi0_pins>; > + status = "okay"; > + > + spi_dev0: spi@0 { > + compatible = "st,m25p80"; > + pl022,com-mode = <1>; > + spi-max-frequency = <10000000>; > + reg = <0>;
reg is always following compatible, not somewhere deep in properties.
> + status = "okay";
okay is by default
> + }; > +};
Best regards, Krzysztof
| ![\](/images/icornerr.gif) |