Messages in this thread | | | Date | Mon, 5 Jun 2023 13:15:36 +0200 | Subject | Re: [PATCH v2 1/6] arm64: zynqmp: Describe TI phy as ethernet-phy-id | From | Michal Simek <> |
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On 5/22/23 16:59, Michal Simek wrote: > TI DP83867 is using strapping based on MIO pins. Tristate setup can > influence PHY address. That's why switch description with ethernet-phy-id > compatible string which enable calling reset. PHY itself setups phy address > after power up or reset. Phy reset is done via gpio. > > Signed-off-by: Michal Simek <michal.simek@amd.com> > --- > > Changes in v2: > - fix typo in commit message > > Checkpatch is reporting issue > warning: DT compatible string "ethernet-phy-id2000.a231" appears un-documented > but it should be fully aligned with > Documentation/devicetree/bindings/net/ethernet-phy.yaml > > c&p more details from v1 version: > Phy has some pins which is using for strapping for phy address after phy > reset or power on. Pretty much it is resistor array which based on > datasheet is decoded to certain phy address. > And because some phy pins are also used as data pin for RGMII they are > connected via MIO pins on a silicon. That's why IO block output setting > really matter here because it changes resistor array and it moves phy > address. > That's why there is a need to do proper IO pin setup and after it call phy > reset to get it to address which was decided by PCB designer. > > --- > .../boot/dts/xilinx/zynqmp-zcu102-revA.dts | 23 +++++++++++------ > .../boot/dts/xilinx/zynqmp-zcu102-revB.dts | 25 +++++++++++-------- > .../boot/dts/xilinx/zynqmp-zcu104-revA.dts | 22 ++++++++++------ > .../boot/dts/xilinx/zynqmp-zcu104-revC.dts | 22 ++++++++++------ > .../boot/dts/xilinx/zynqmp-zcu106-revA.dts | 22 ++++++++++------ > .../boot/dts/xilinx/zynqmp-zcu111-revA.dts | 22 ++++++++++------ > 6 files changed, 90 insertions(+), 46 deletions(-) > > diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts > index 230ef94d5dcb..f36353a51863 100644 > --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts > +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts > @@ -2,7 +2,8 @@ > /* > * dts file for Xilinx ZynqMP ZCU102 RevA > * > - * (C) Copyright 2015 - 2021, Xilinx, Inc. > + * (C) Copyright 2015 - 2022, Xilinx, Inc. > + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. > * > * Michal Simek <michal.simek@amd.com> > */ > @@ -200,13 +201,19 @@ &gem3 { > phy-mode = "rgmii-id"; > pinctrl-names = "default"; > pinctrl-0 = <&pinctrl_gem3_default>; > - phy0: ethernet-phy@21 { > - reg = <21>; > - ti,rx-internal-delay = <0x8>; > - ti,tx-internal-delay = <0xa>; > - ti,fifo-depth = <0x1>; > - ti,dp83867-rxctrl-strap-quirk; > - /* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */ > + mdio: mdio { > + #address-cells = <1>; > + #size-cells = <0>; > + phy0: ethernet-phy@21 { > + #phy-cells = <1>; > + compatible = "ethernet-phy-id2000.a231"; > + reg = <21>; > + ti,rx-internal-delay = <0x8>; > + ti,tx-internal-delay = <0xa>; > + ti,fifo-depth = <0x1>; > + ti,dp83867-rxctrl-strap-quirk; > + reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; > + }; > }; > }; > > diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts > index 63419deb5b33..3c28130909bc 100644 > --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts > +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts > @@ -2,7 +2,8 @@ > /* > * dts file for Xilinx ZynqMP ZCU102 RevB > * > - * (C) Copyright 2016 - 2021, Xilinx, Inc. > + * (C) Copyright 2016 - 2022, Xilinx, Inc. > + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. > * > * Michal Simek <michal.simek@amd.com> > */ > @@ -16,16 +17,20 @@ / { > > &gem3 { > phy-handle = <&phyc>; > - phyc: ethernet-phy@c { > - reg = <0xc>; > - ti,rx-internal-delay = <0x8>; > - ti,tx-internal-delay = <0xa>; > - ti,fifo-depth = <0x1>; > - ti,dp83867-rxctrl-strap-quirk; > - /* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */ > + mdio: mdio { > + phyc: ethernet-phy@c { > + #phy-cells = <0x1>; > + compatible = "ethernet-phy-id2000.a231"; > + reg = <0xc>; > + ti,rx-internal-delay = <0x8>; > + ti,tx-internal-delay = <0xa>; > + ti,fifo-depth = <0x1>; > + ti,dp83867-rxctrl-strap-quirk; > + reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; > + }; > + /* Cleanup from RevA */ > + /delete-node/ ethernet-phy@21; > }; > - /* Cleanup from RevA */ > - /delete-node/ ethernet-phy@21; > }; > > /* Fix collision with u61 */ > diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts > index d178a4f898c9..3fd47725c2c8 100644 > --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts > +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts > @@ -2,7 +2,8 @@ > /* > * dts file for Xilinx ZynqMP ZCU104 > * > - * (C) Copyright 2017 - 2021, Xilinx, Inc. > + * (C) Copyright 2017 - 2022, Xilinx, Inc. > + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. > * > * Michal Simek <michal.simek@amd.com> > */ > @@ -109,12 +110,19 @@ &gem3 { > phy-mode = "rgmii-id"; > pinctrl-names = "default"; > pinctrl-0 = <&pinctrl_gem3_default>; > - phy0: ethernet-phy@c { > - reg = <0xc>; > - ti,rx-internal-delay = <0x8>; > - ti,tx-internal-delay = <0xa>; > - ti,fifo-depth = <0x1>; > - ti,dp83867-rxctrl-strap-quirk; > + mdio: mdio { > + #address-cells = <1>; > + #size-cells = <0>; > + phy0: ethernet-phy@c { > + #phy-cells = <1>; > + compatible = "ethernet-phy-id2000.a231"; > + reg = <0xc>; > + ti,rx-internal-delay = <0x8>; > + ti,tx-internal-delay = <0xa>; > + ti,fifo-depth = <0x1>; > + ti,dp83867-rxctrl-strap-quirk; > + reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; > + }; > }; > }; > > diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts > index 38b11594c074..4f6429caecff 100644 > --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts > +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts > @@ -2,7 +2,8 @@ > /* > * dts file for Xilinx ZynqMP ZCU104 > * > - * (C) Copyright 2017 - 2021, Xilinx, Inc. > + * (C) Copyright 2017 - 2022, Xilinx, Inc. > + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. > * > * Michal Simek <michal.simek@amd.com> > */ > @@ -114,12 +115,19 @@ &gem3 { > phy-mode = "rgmii-id"; > pinctrl-names = "default"; > pinctrl-0 = <&pinctrl_gem3_default>; > - phy0: ethernet-phy@c { > - reg = <0xc>; > - ti,rx-internal-delay = <0x8>; > - ti,tx-internal-delay = <0xa>; > - ti,fifo-depth = <0x1>; > - ti,dp83867-rxctrl-strap-quirk; > + mdio: mdio { > + #address-cells = <1>; > + #size-cells = <0>; > + phy0: ethernet-phy@c { > + #phy-cells = <1>; > + compatible = "ethernet-phy-id2000.a231"; > + reg = <0xc>; > + ti,rx-internal-delay = <0x8>; > + ti,tx-internal-delay = <0xa>; > + ti,fifo-depth = <0x1>; > + ti,dp83867-rxctrl-strap-quirk; > + reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; > + }; > }; > }; > > diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts > index 8af0879806cf..8c3fa3fe28d5 100644 > --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts > +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts > @@ -2,7 +2,8 @@ > /* > * dts file for Xilinx ZynqMP ZCU106 > * > - * (C) Copyright 2016 - 2021, Xilinx, Inc. > + * (C) Copyright 2016 - 2022, Xilinx, Inc. > + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. > * > * Michal Simek <michal.simek@amd.com> > */ > @@ -212,12 +213,19 @@ &gem3 { > phy-mode = "rgmii-id"; > pinctrl-names = "default"; > pinctrl-0 = <&pinctrl_gem3_default>; > - phy0: ethernet-phy@c { > - reg = <0xc>; > - ti,rx-internal-delay = <0x8>; > - ti,tx-internal-delay = <0xa>; > - ti,fifo-depth = <0x1>; > - ti,dp83867-rxctrl-strap-quirk; > + mdio: mdio { > + #address-cells = <1>; > + #size-cells = <0>; > + phy0: ethernet-phy@c { > + #phy-cells = <1>; > + reg = <0xc>; > + compatible = "ethernet-phy-id2000.a231"; > + ti,rx-internal-delay = <0x8>; > + ti,tx-internal-delay = <0xa>; > + ti,fifo-depth = <0x1>; > + ti,dp83867-rxctrl-strap-quirk; > + reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; > + }; > }; > }; > > diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts > index f76687914e30..0d9b6081dff6 100644 > --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts > +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts > @@ -2,7 +2,8 @@ > /* > * dts file for Xilinx ZynqMP ZCU111 > * > - * (C) Copyright 2017 - 2021, Xilinx, Inc. > + * (C) Copyright 2017 - 2022, Xilinx, Inc. > + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. > * > * Michal Simek <michal.simek@amd.com> > */ > @@ -172,12 +173,19 @@ &gem3 { > phy-mode = "rgmii-id"; > pinctrl-names = "default"; > pinctrl-0 = <&pinctrl_gem3_default>; > - phy0: ethernet-phy@c { > - reg = <0xc>; > - ti,rx-internal-delay = <0x8>; > - ti,tx-internal-delay = <0xa>; > - ti,fifo-depth = <0x1>; > - ti,dp83867-rxctrl-strap-quirk; > + mdio: mdio { > + #address-cells = <1>; > + #size-cells = <0>; > + phy0: ethernet-phy@c { > + #phy-cells = <1>; > + compatible = "ethernet-phy-id2000.a231"; > + reg = <0xc>; > + ti,rx-internal-delay = <0x8>; > + ti,tx-internal-delay = <0xa>; > + ti,fifo-depth = <0x1>; > + ti,dp83867-rxctrl-strap-quirk; > + reset-gpios = <&tca6416_u22 6 GPIO_ACTIVE_LOW>; > + }; > }; > }; >
Applied. M -- Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Xilinx Microblaze Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP/Versal ARM64 SoCs U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal/Versal NET SoCs TF-A maintainer - Xilinx ZynqMP/Versal/Versal NET SoCs
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