Messages in this thread | | | Date | Mon, 26 Jun 2023 11:38:59 +0200 | From | Sascha Hauer <> | Subject | Re: [PATCH] clk: rockchip: rk3568: Add PLL rate for 101MHz |
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On Wed, Jun 14, 2023 at 04:47:16PM +0300, Alibek Omarov wrote: > This patch adds PLL setting for not so common resolution as 1920x720-50.00, > which can be set using 2500 horizontal signals and 808 vertical. > > Signed-off-by: Alibek Omarov <a1ba.omarov@gmail.com>
Reviewed-by: Sascha Hauer <s.hauer@pengutronix.de>
> --- > drivers/clk/rockchip/clk-rk3568.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/clk/rockchip/clk-rk3568.c b/drivers/clk/rockchip/clk-rk3568.c > index f85902e2590c..5dae960af4ce 100644 > --- a/drivers/clk/rockchip/clk-rk3568.c > +++ b/drivers/clk/rockchip/clk-rk3568.c > @@ -79,6 +79,7 @@ static struct rockchip_pll_rate_table rk3568_pll_rates[] = { > RK3036_PLL_RATE(135000000, 2, 45, 4, 1, 1, 0), > RK3036_PLL_RATE(119000000, 3, 119, 4, 2, 1, 0), > RK3036_PLL_RATE(108000000, 2, 45, 5, 1, 1, 0), > + RK3036_PLL_RATE(101000000, 1, 101, 6, 4, 1, 0),
refdiv = 1 fbdiv = 101 postdiv1 = 6 postdiv2 = 4
((24000000/1)*101)/6/4 = 101000000
Ok.
Sascha
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